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Volumn , Issue , 2010, Pages 111-114

A 120-Gbit/s 520-mVPP multiplexer IC using 1-μm self-aligned InP/InGaAs/InP DHBT with emitter mesa passivation ledge

Author keywords

[No Author keywords available]

Indexed keywords

2:1 MULTIPLEXERS; BROADBAND IMPEDANCE; CIRCUIT DESIGNS; DOUBLE HETEROSTRUCTURE BIPOLAR TRANSISTOR; POWER DISSIPATION; PRACTICAL USE; RETIMING; SELF-ALIGNED;

EID: 77955960636     PISSN: 10928669     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICIPRM.2010.5515958     Document Type: Conference Paper
Times cited : (4)

References (17)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.