Over-100-Gb/s 1:2 demultiplexer based on InP HBT technology

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 11, 2007, Pages 2594-2599

  Suzuki, Yasuyuki ^a   Mamada, Masayuki ^a   Yamazaki, Zin ^a  

^a NEC CORPORATION   (Japan)

Author keywords

Demultiplexing; Error free operation; Flip flops; Heterojunction bipolar transistors; High speed integrated circuits; InP HBT; Multiplexing; optical communication

Indexed keywords

BROADBAND IMPEDANCES; CLOCK DISTRIBUTIONS; DATA RATES; DEMULTIPLEXER; ERROR-FREE OPERATION; FLIP-FLOPS; HIGH-SPEED INTEGRATED CIRCUITS; HIGH-SPEED OPERATIONS; IC CHIPS; INP HBT; INTERCONNECTION LINES; OUTPUT VOLTAGE SWINGS; PHASE CONSTANTS; SIGNAL QUALITIES; TIMING MARGINS;

BICMOS TECHNOLOGY; BIPOLAR TRANSISTORS; DEMULTIPLEXING; FLIP FLOP CIRCUITS; INTEGRATED CIRCUITS; JITTER; MULTIPLEXING; OPTICAL COMMUNICATION; PHOTONICS;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 57849098456     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.907215     Document Type: Conference Paper

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