A load-balanced routing scheme for NoC-based systems-on-chip

Proceedings - 2010 First Workshop on Hardware and Software Implementation and Control of Distributed MEMS, dMEMS 2010

Volumn , Issue , 2010, Pages 72-77

  Yazdi, Mahdi Asefi ^a   Modarressi, Mehdi ^a   Sarbazi Azad, Hamid ^a  

^a NONE

Author keywords

Load balancing; MEMS; Network on chip; Performance; Power consumption; Routing; Run time route selection; System on chip

Indexed keywords

LOAD-BALANCING; NETWORK ON CHIP; PERFORMANCE; POWER CONSUMPTION; ROUTING; RUNTIMES; SYSTEM ON CHIPS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DIGITAL DEVICES; EMBEDDED SYSTEMS; FAULT TOLERANCE; MICROPROCESSOR CHIPS; NETWORK ROUTING; PARALLEL ARCHITECTURES; PROGRAMMABLE LOGIC CONTROLLERS; QUALITY ASSURANCE; SERVERS; VLSI CIRCUITS;

TRAFFIC CONGESTION;

EID: 77955820273     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dMEMS.2010.18     Document Type: Conference Paper

References (23)

1. J. Owens, W. J. Dally, R. Ho, D.N. Jayasimha, S.W. Keckler, and L. S. Peh, "Research challenges for on-chip interconnection networks", IEEE Micro, Vol. 27, No. 5, 2007, pp. 96-108.
2. L. Benini, and G. De Micheli, "Networks on chip: a new paradigm for systems on chip design", IEEE Computer, Vol. 35, No. 1, 2001, pp.70-78.
3. W. J. Dally, and B. Towles, Principles and practices of interconnection networks, Morgan Kaufmann Publishers, 2004.
4. J. Hu, R. Marculescu, "Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures", In Proceedings of DATE, 2003, pp. 668-693.
5. H. R. Kenneth, Discrete Mathematics and Its Applications, 2005, 5th Edition. Addison Wesley.
6. L. Smit, G. Smit, J. Hurink, H. Broersma, D. Paulusma, and P. Wolkotte, "Run-time mapping of applications to a heterogeneous reconfigurable tiled system on chip architecture", in Proc. of the IEEE int. Conf. on Field-Programmable Technology, pp. 421-424, 2004.
7. E. Carvalho, N. Calazans, and F. Moraes, "Heuristics for dynamic task mapping in NoC-based heterogeneous MPSoCs", in Proc. of the 18th IEEE int. workshop on Rapid System Prototyping, pp. 34-40, 2007.
8. K. Goossens, J. Dielissen, and A.Radulescu, "The Æthereal Network on Chip: Concepts, Architectures, and Implementations", in IEEE Design and Test of Computers, Vol. 22, No. 5, Sept-Oct 2005, pp. 414-421.
9. P. Guerrier, and A. Greiner, "A generic architecture for on-chip packet-switched interconnections", in Proceedings of the Design Automation and Test in Europe (DATE), 2000, pp. 250-256.
10. W. J. Dally, and B. Towles, "Route packets, not wires: On-chip interconnection networks", In Proceedings of Design Automation Conference (DAC), 2001, 684-689.
11. A. Jantsch, and H. Tenhunen, Networks on Chip, Kluwer Academic Publishers, 2003.
12. M. Modarressi, and H. Sarbazi-Azad, "Power-aware mapping for reconfigurable NoC architectures", in Proceedings of ICCD, 2007, pp. 417-422.
13. T. Bjerregaard, and S. Mahadevan, "A survey of research and practices of network-on-chip", ACM Computing Surveys, Vol. 38, No. 1, 12006, pp. 1-51.
14. P. Gratz, B. Grot, and S. W. Keckler, "Regional congestion awareness for load balance in networks-on-chip", in Proc. of the 14th IEEE International Symposium on High-Performance Computer Architecture, 2008.
15. M. A. Kinsy, M. H. Cho, T. Wen, E. Suh, M. van Dijk, S. Devadas, "Application-aware deadlock-free oblivious routing", in ACM SIGARCH Computer Architecture News, Vol. 37, No.3, June 2009.
16. C. Bobda, A.Ahmadinia, M. Majer, J. Teich, S. P. Fekete, J. van der Veen, "DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices", in Proc. of FPL, 2005, pp. 153-158.
17. C.J. Glass, L.M. Ni, "The turn model for adaptive routing", in Proc. 19th Int'l Symposium on Computer Architecture, May 1992, pp. 278-287.
18. J. van den Brand, et al, "Congestion-controlled best-effort communication for networks-on-chip", in Proc. of DATE, 2007, pp. 948-953.
19. M. Majer, C. Bobda, A. Ahmadinia, J. Teich, "Packet Routing in Dynamically Changing Networks on Chip", in Proc. of IPDPS, 2005.
20. J. Hu, R. Marculescu, "DyAD - Smart routing for networks-on-chip, " in Proc. of DAC, 2004, pp. 260-263.
21. SPLASH-2, http://www.flash.stanford.edu/apps/SPLASH/.
22. Xmulator NoC Simulator, from http://www.xmulator.org, 2009.
23. A. Kahng, B. Li, L. Peh and K. Samadi, "ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration", in Proceedings of Design Automation and Test in Europe (DATE), France, 2009.