Heuristics for dynamic task mapping in NoC-based heterogeneous MPSoCs

Proceedings of the International Workshop on Rapid System Prototyping

Volumn , Issue , 2007, Pages 34-40

  Carvalho, Ewerson ^a   Calazans, Ney ^a   Moraes, Fernando ^a  

^a PONTIFICAL CATHOLIC UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

CONGESTION CONTROL (COMMUNICATION); COST FUNCTIONS; HEURISTIC METHODS; REAL TIME SYSTEMS; SCHEDULING; VLSI CIRCUITS;

CONGESTION-AWARE MAPPING; DYNAMIC WORKLOADS; STATIC MAPPING;

MULTIPROCESSING SYSTEMS;

EID: 34548717064     PISSN: 10746005     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RSP.2007.26     Document Type: Conference Paper

References (11)

1. Jerraya, A.; Tenhunen, H.; Wolf, W. Guest Editors' Introduction: Multiprocessor Systems-on-Chips. IEEE Computer, v.38(7), 2005.
2. Hu, J.; Marculescu, R. Energy- and Performance-Aware Mapping for Regular NoC Architectures. IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, v.24(4), 2005.
3. Marcon, C.; Borin, A.; Susin, A.; Carro, L.; Wagner, F. Time and Energy Efficient Mapping of Embedded Applications onto NoCs. ASP-DAC, 2005.
4. Nollet, V.; Marescaux, T.; Avasare, P.; Mignolet, J-Y. Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles. DATE, 2005.
5. Bertozzi, S.; Acquaviva, A.; Bertozzi, D.; Poggiali, A. Supporting task migration in multi-processor systems-on-chip: a feasibility study. DATE, 2006.
6. Ahmadinia, A.; Teich, J. Speeding up Online Placement for XILINX FPGAs by Reducing Configuration Overhead. VLSI-SoC, 2003.
7. Handa, M.; Vemuri, R. An Integrated Online Scheduling and Placement Methodology. FPL, 2004.
8. Tabero, J.; Septién, J.; Mecha, H.; Mozos, D. A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management. FPL, 2004.
9. Ruggiero, M.; Guerri, A.; Bertozzi, D.; Poletti, F.; Milano, M. Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip. DATE, 2006.
10. Marcon, C.; Calazans, N.; Moraes, F.; Susin, A.; Reis, I.; Hessel, F. Exploring NoC mapping strategies: an energy and timing aware technique. DATE, 2005.
11. Kalte, H.; Lee, G.; Porrmann, M. Context Saving and Restoring for Multitasking in Reconfigurable Systems. FPL, 2005.