Chip-package interactions: Some combined package effects on copper/low-k interconnect delaminations

Proceedings - 2008 2nd Electronics Systemintegration Technology Conference, ESTC

Volumn , Issue , 2008, Pages 713-718

  Fiori, Vincent ^a   Gallois Garreignot, Sébastien ^a   Tavernier, Clement ^a   Jaouen, Hervé ^a   Juge, André ^a  

^a STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ADHESIVES; DELAMINATION; DIELECTRIC MATERIALS; DIES; ELECTRONIC EQUIPMENT MANUFACTURE; ELECTRONICS PACKAGING; GLUES; GLUING; TECHNOLOGICAL FORECASTING; THREE DIMENSIONAL;

BALL GRID ARRAY PACKAGES; DIE ATTACH; FEATURE SIZES; FRACTURE RISKS; IC CHIPS; IMD LAYERS; INTERCONNECT LEVELS; MOORE'S LAWS; PACKAGE MODELS; PARAMETERIZED; POST-PROCESSING; PRELIMINARY ANALYSIS; PRODUCT CRISIS; RELEASED ENERGIES; SHEAR MODES; TECHNOLOGY DEVELOPMENTS; THERMOMECHANICAL STRESSES;

PACKAGING;

EID: 58149094505     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESTC.2008.4684438     Document Type: Conference Paper

References (10)

1. Integration of a Mechanically Reliable 65-nm node technology for low-k and ULK Interconnects with various Substrate and Package Types, Goldberg C., IEEE, 2005.
2. Reliability of Advanced Interconnect Structures: New Materials and Length Scale Challenges, Dauskardt, R.H., Stroband, S., Stanford Material science and Engineering report, 2002.
3. Reliability Challenges accompagnied with interconnect downscaling and ultra low-k dielectrics, Hoofman R.J.O.M, IEEE, 2005.
4. Impact of Low-k dielectrics on microelectronics reliability, Don Scansen, IEEE CCECE/CCGEI, Saskatoon, May 2005.
5. Chip-packaging interaction: a critical concern for Cu/low k packaging, G.Wang et al., Microelectronics Reliability 45 (2005) 1079-1093.
6. Evaluation of Die Edge Cracking in Flip-Chip PBGA Packages. Lei L. Mercado et Al., IEEE Trans. On Components and Packaging Technologies, vol. 26, n.4, dec.2003.
7. Multi-level Numerical and Experimental Analysis on the Reliability of Cu/low-k Interconnection in FCBGA Package, V.Fiori et al., ECTC 2006.
8. 3D Multi Scale Modeling of Wire Bonding Induced Peeling in Cu/Low-k Interconnects: Application of an Energy Based Criteria and Correlations with Experiments. V.Fiori et al., ECTC 2007.
9. Analysis of Cu/low-k Bond Pad Delamination by using a Novel Failure Index, M.A.J. van Gils et al, Microelectronics Reliability, 2006.
10. Numerical Analysis of the Reliability of Cu/low-k Bond Pad Interconnections Under Wire Pull Test Application of a 3D Energy Based Failure Criteria, Gallois-Garreignot S., Eurosime conference 2007.