A systematic underfill selection methodology for fine pitch Cu/low-k FCBGA package

Proceedings of the Electronic Packaging Technology Conference, EPTC

Volumn , Issue , 2007, Pages 646-651

  Ong, Xuefen ^a,b,c   Ho, Soon Wee ^a   Ong, Yue Ying ^a   Wai, Leong Ching ^a   Vaidyanathan, Kripesh ^a   Lim, Yeow Kheng ^b   Yeo, David ^b   Chan, Kai Chong ^b   Tan, Juan Boon ^b   Sohn, Dong Kyun ^b   Hsia, Liang Choo ^b   Chen, Zhong ^c  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b CHARTERED SEMICONDUCTOR MANUFACTURING LTD   (Singapore)

^c NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS PACKAGING; TECHNOLOGY;

FINE PITCH; PACKAGING TECHNOLOGIES; UNDERFILL; UNDERFILL ENCAPSULANTS;

ELECTRONIC EQUIPMENT MANUFACTURE;

EID: 50049123595     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2007.4469684     Document Type: Conference Paper

References (5)

1. th Electronic Components and Technology Conf 2006, pp. 1595-1603.
2. 4h Electronic Components and Technology Conf., 2004, Vol. 1, No. 1, pp. 175-9.
3. Guotao Wang, Ho, P.S., Groothuis S., "Chip-packaging interaction: a critical concern for Cu/low k packaging," Microelectronics Reliability, Vol. 45, No. 7-8 (2005), pp. 1079-93.
4. ASTM designation (D5045-99): Standard Test Methods for Plane-Strain Fracture Toughness and Strain Energy Release Rate of Plastic Materials
5. W. M. Tsai, P. N. Houston, D. F. Baldwin, "Flux-underfill Compatibility and Failure Mode Analysis in High Yield Flip Chip Process," In Proceeding of IEEE / CPMT Int. Electronics Manufacturing Technology Symposium, Santa Clara, CA, 2000, p. 160-167