Chip-packaging interaction: A critical concern for Cu/low k packaging

Microelectronics Reliability

Volumn 45, Issue 7-8, 2005, Pages 1079-1093

  Wang, Guotao ^a   Ho, Paul S ^a   Groothuis, Steven ^b  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b MICRON TECHNOLOGY INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COPPER; CRACK INITIATION; DELAMINATION; EUTECTICS; FINITE ELEMENT METHOD; FLIP CHIP DEVICES; INTERFEROMETRY; MOIRE FRINGES; PHASE SHIFT; STRESS CONCENTRATION; SURFACE CHEMISTRY; THERMAL STRESS;

PORTABLE ENGINEERING MOIRÉ INTERFEROMETER (PEMI); ROOM TEMPERATURE; THERMAL DEFORMATIONS; THERMAL LOADING;

CHIP SCALE PACKAGES;

EID: 20344395335     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2004.12.008     Document Type: Article

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