A 0.11 μm CMOS technology featuring copper and very low k interconnects with high performance and reliability

Microelectronics Reliability

Volumn 42, Issue 1, 2002, Pages 15-25

  Takao, Yoshihiro ^a   Kudo, Hiroshi ^a   Mitani, Junichi ^a   Kotani, Yoshiyuki ^a   Yamaguchi, Satoshi ^a   Yoshie, Keizaburo ^a   Sukegawa, Kazuo ^a   Naori, Nobuhisa ^a   Asai, Satoru ^a   Kawano, Michiari ^b   Nagano, Takashi ^b   Yamamura, Ikuhiro ^b   Uematsu, Masaya ^b   Nagashima, Naoki ^b   Kadomura, Shingo ^b  

^a FUJITSU LABORATORIES LTD   (Japan)

^b SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; GATES (TRANSISTOR); LITHOGRAPHY; MOSFET DEVICES; RELIABILITY; STATIC RANDOM ACCESS STORAGE;

DRAIN CURRENTS;

CMOS INTEGRATED CIRCUITS;

EID: 0036133673     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(01)00233-5     Document Type: Article

References (17)

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17. A 0.13 μm CMOS platform with Cu/low-k interconnects for system on chip applications