Challenges in the assembly of large die, high bump density Pb-free flip chip packages

Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium

Volumn , Issue , 2007, Pages 346-351

  Libres, Jeremias ^a   Robinson, Karen ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

Flux compatibility; Lead free assembly; Underfill challenges

Indexed keywords

DIE SIZE; ELECTRONICS MANUFACTURING; FLIP CHIPPING; FLIP-CHIP BUMPING; FLIP-CHIP PACKAGING; FLUX COMPATIBILITY; HIGH-DENSITY; LEAD FREE ASSEMBLY; LEAD-FREE; MAJOR FACTOR; PAD SURFACE; PB-FREE; PROCESS MARGINS; PROCESS WINDOWS; REFLOW TEMPERATURES; SELECTION PROCESSES; SOLDERING PERFORMANCE; UNDERFILL; UNDERFILL CHALLENGES; UNDERFILL CURING; UNDERFILL FLOW;

ASPECT RATIO; BRAZING; CURING; DIES; DRYING; FLIP CHIP DEVICES; LEAD; LEAD ALLOYS; MANUFACTURE; OPTICAL ENGINEERING; SOLDERING; TECHNOLOGY; WELDING;

FLUXES;

EID: 48149104382     PISSN: 10898190     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEMT.2007.4417087     Document Type: Conference Paper

References (4)

1. F. Zhang, M. Li, W.T. Chen, "An Investigation Into the Effects of Flux Residues on Properties of Underfill Materials for Flip Chip Packages", IEEE Transactions on Components and Packaging Technologies", Vol. 26, No. 1, Dec. 2003
2. W. H. Leong, "Developing an Underfill Process for Dense Flip Chip Applications", 1996 IEEE/CPMT International Electronics Manufacturing Symposium.
3. R. Chaware, L. Stiborek, J. Libres, M. Marquez, C. Odegard, M. Cowens, M. Ventakeswaran, "Effect of Compatibility Between Fluxes and Cyanate Ester Underfill on Lead Free Flip Chip Assembly and Reliability, 2005 IMAPS Proceedings.
4. J. Wang, "The Effect of Flux Residue and Substrate Wettability On Underfill Flow Process in Flip Chip Packages", 2006 IEEE/ECTC pp. 467-473