Advanced HiCTE flip chip packaging of 90-nm Cu/Low-K chips: Underfill, novel terminal pad structures, and processing optimization

Journal of Electronic Materials

Volumn 34, Issue 7, 2005, Pages 977-993

  Chungpaiboonpatana, Surasit ^a,b   Shi, Frank G ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b Mindspeed ^*  (United States)

Author keywords

Cu Low K flip chip; Reliability; Stress relieved passivation; Underfill interfaces

Indexed keywords

COPPER; CRACK INITIATION; FLIP CHIP DEVICES; METALLURGY; OPTIMIZATION; PASSIVATION; POROSITY; RELIABILITY; SCANNING ELECTRON MICROSCOPY;

CU/LOW-K FLIP CHIP; PAD STRUCTURES; STRESS-RELIEVED PASSIVATION; UNDERFILL INTERFACES;

CHIP SCALE PACKAGES;

EID: 23244459488     PISSN: 03615235     EISSN: None     Source Type: Journal    
DOI: 10.1007/s11664-005-0085-6     Document Type: Article

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