A framework for scalable postsilicon statistical delay prediction under process variations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 28, Issue 1, 2009, Pages 1201-1212

  Liu, Qunzeng ^a   Sapatnekar, Sachin S ^a  

^a University of Minnesota   (United States)

Author keywords

Algorithms; Circuit analysis; Design automation; Timing

Indexed keywords

BENCHMARK SUITES; CIRCUIT ANALYSIS; DELAY ANALYSIS; MONTE CARLO SIMULATION; NANO SCALE; NOVEL METHODS; ON CHIPS; PARAMETER VARIATION; POST-SILICON; PREDICTION TECHNIQUES; PROBABILITY DENSITY FUNCTION (PDF); PROCESS VARIATION; STANDARD DEVIATION; STATISTICAL CIRCUIT ANALYSIS; STATISTICAL TIMING ANALYSIS; TEST STRUCTURE;

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; DIES; MONTE CARLO METHODS; PACKET NETWORKS; PROBABILITY DENSITY FUNCTION; PROBABILITY DISTRIBUTIONS; TIME MEASUREMENT; TIMING CIRCUITS;

ELECTRIC NETWORK ANALYSIS;

EID: 77955216099     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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