Characterization of microprocessor chip stress distributions during component packaging and thermal cycling

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2010, Pages 1281-1295

  Roberts, Jordan ^a   Hussain, Safina ^a   Kaysar Rahim, M ^a   Motalab, Mohammad ^a   Suhling, Jeffrey C ^a   Jaeger, Richard C ^a   Lall, Pradeep ^a   Zhang, Ron ^b  

^a AUBURN UNIVERSITY   (United States)

^b ORACLE CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASSEMBLY OPERATIONS; ASSEMBLY PROCESS; CERAMIC CHIPS; CERAMIC SUBSTRATES; COMPONENT PACKAGING; CRITICAL LOCATION; DATA ACQUISITION HARDWARE; DIE DEVICES; DIE STRESS; DIE SURFACE; FINITE ELEMENT MODELS; IN-SITU; INDUCED STRESS; LEAD FREE SOLDERS; LOW STRESS; ON CHIPS; PACKAGING PROCESS; PIEZORESISTIVE STRESS SENSORS; QUASI-STATIC; SENSOR RESISTANCE; SILICON DIE; SOLDER REFLOW; STRESS COMPONENT; STRESS DISTRIBUTION; TEMPERATURE CHANGES; TEST CHIPS; THREE DIMENSIONAL STRESS STATE; UNDERFILLS;

CERAMIC MATERIALS; CURING; DIES; FINITE ELEMENT METHOD; LEAD; MICROPROCESSOR CHIPS; PACKAGING; SENSORS; SILICON WAFERS; SOLDERING ALLOYS; STRESS CONCENTRATION; TESTING; THERMAL CYCLING;

CHIP SCALE PACKAGES;

EID: 77955197315     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2010.5490655     Document Type: Conference Paper

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