In process stress analysis of flip-chip assemblies during underfill cure

Microelectronics Reliability

Volumn 40, Issue 7, 2000, Pages 1181-1190

  Palaniappan, P ^a   Baldwin, Daniel F ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CURING; ELECTRONICS PACKAGING; GLASS TRANSITION; INTEGRATED CIRCUIT TESTING; RESIDUAL STRESSES; STRESS ANALYSIS; STRESS RELAXATION;

UNDERFILLS;

FLIP CHIP DEVICES;

EID: 0034224530     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(00)00045-7     Document Type: Article

References (15)

1. Palaniappan P, Baldwin DF. Process stress analysis of flip chip assemblies during underfill cure. Applications of experimental mechanics to electronic packaging, vol. EEP-22/AMD-226, NY: ASME, 1997. p. 7-14.
2. Palaniappan P, Selman P, Baldwin DF, Wu J, Wong CP. Correlation of flip chip underfill process parameters and material properties with in-process stress generation. IEEE Trans CPMT-C 1999;20:53-62.
3. Sweet JN, Peterson DW, Tuck MR, Green JM. Assembly Test Chip Ver. 04(ATC04) Description and User Guide, Sandia National Laboratories. In: SAND93-1901, August 1993. p. 2-27.
4. Sweet JN, Peterson DW, Emerson JA, Burchett SN. Experimental measurement and finite element calculations for liquid encapsulated ATC04 assembly test chips. In: Applications of Experimental Mechanics to Electronic Packaging, vol. EPP13, NY: ASME, 1995. p. 12-7.
5. Peterson DW, Sweet JN, Burchett SN, Hsia A. Stresses from flip-chip assembly and underfill - measurements with the ATC4.1 assembly test chip and analysis by finite element method. In: Proc 1997 Elec Comp Tech Conf, ECTC'97, San Jose, CA, May 1997. p. 134-43.
6. Bittle DA, Suhling JC, Beaty RE, Jaeger RC, Johnson RW. Piezoresistive stress sensors for structural analysis of electronics packages. J Electron Packag 1991;113:203.
7. Spencer J, Schroen WH, Bednarz GA, Bryan JA, Metzgar TD, Cleveland RD. New quantitative measurements of IC stress introduced by plastic packages. In: Proc 19th Int Reliab Phys Symp IEEE, 1981. p. 74-80.
8. Gee SA, Akylas VR, van den Bogert WF. The design and calibration of a semiconductor strain gauge array. In: Proc 1988 IEEE Int Conf Microelectron Test Struct ICTMS'88, 1988. p. 185-91.
9. Gee SA, van den Bogert WF, Akylas VR. Strain gauge mapping of die surface stresses. IEEE Trans CPMT 1989;12:587-93.
10. Nguyen LT. Reliability of postmolded IC packages. J Electron Packag 1993;115:346-55.
11. Peterson DW, Sweet JN, Burchett SN. Validating theoretical calculations of thermomechanical stress and deformation using the ATC4.1 flip-chip test vehicle. Surface Mount International'97, San Jose, CA, September 1997.
12. Suhir E. Die attachment design and its influence on thermal stresses in the die and the attachment. In: Proc 1987 Elec Comp Conf, 1987. p. 508-17.
13. Suhir E, Segelken JM. Mechanical behavior of flip chip encapsulants. J Electron Packag 1991;112:327-32.
14. Palaniappan P. In-process stress analysis of flip chip assemblies during underfill cure and environmental stress testing. MS Thesis, Mech Engng Georgia Inst of Tech Atlanta, GA 1998.
15. Sylvester MF, Banks DR, Kern RL, Pofahl RG. Thermomechanical reliability assessment of large organic flip-chip ball grid array packages. In: Proc 1998 Elec Comp Tech Conf, ECTC'98, May 1998. p. 851-60.