A 1-GS/s 6-bit 6.7-mW ADC in 65-nm CMOS

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2009, Pages 287-290

  Yang, Jing ^a   Naing, Thura Lin ^a   Brodersen, Bob ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Analog to digital conversion; Asynchronous logic circuits; Binary successive approximation algorithm; Cognitive radios; Semi close loop; Time interleaving

Indexed keywords

ASYNCHRONOUS LOGIC CIRCUITS; CLOSE LOOP; COGNITIVE RADIO; SUCCESSIVE APPROXIMATIONS; TIME-INTERLEAVING;

ANALOG CIRCUITS; ANALOG TO DIGITAL CONVERSION; APPROXIMATION ALGORITHMS; APPROXIMATION THEORY; DIGITAL CIRCUITS; DIGITAL SIGNAL PROCESSING; INTEGRATED CIRCUITS; MULTICARRIER MODULATION; RADIO; SIMULATED ANNEALING; SWITCHING CIRCUITS; TIME VARYING SYSTEMS;

LOGIC CIRCUITS;

EID: 74049100912     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2009.5280861     Document Type: Conference Paper

References (5)

1. E. Alpman, H. Lakdawala, L.R. Carley, K. Soumyanath, "A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP Digital CMOS", IEEE ISSCC 2009 Dig. Of Tech. Paper, pp. 65-77. Feb. 2009
2. Y. Lin, S. Chang, Y. Liu, C. Liu, G. Huang, "A 5b 800MS/s 2mW Asynchronous Binary-Search ADC in 65nm CMOS
3. J. Yang, R.W. Brodersen, "Spatial Channel Characterization for Cognitive Radios", MS thesis, 2004
4. J. Yang, R.W. Brodersen, and D. Tse, "Addressing the Dynamic Range Problem in Cognitive Radios", IEEE International Conference on Communications, pp. 5183 - 5188, June, 2007.
5. S. W. M. Chen and R. W. Brodersen, "A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13 um CMOS," IEEE, ISSCC 2006, Dig. of Tech. Papers, pp. 574-575. Feb. 2006.