A 6-bit, 1.2 GHz interleaved SAR ADC in 90nm CMOS

PRIME 2006: 2nd Conference on Ph.D. Research in MicroElectronics and Electronics - Proceedings

Volumn , Issue , 2006, Pages 301-304

  Dondi, Silvia ^a   Vecchi, Davide ^a   Boni, Andrea ^a   Bigi, Marco ^a  

^a UNIVERSITY OF PARMA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; APPROXIMATION THEORY; BANDWIDTH; CAPACITORS; ELECTRIC POWER UTILIZATION; FREQUENCY RESPONSE;

ANALOG-TO-DIGITAL CONVERTERS; SAMPLING FREQUENCY; SUCCESSIVE APPROXIMATIONS REGISTER;

CMOS INTEGRATED CIRCUITS;

EID: 34547322118     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. C. Sandner et al. "A 6bit, 1.2 GSps Low-Power Flash-ADC in 0.13μm Digital CMOS", Proc. of IEEE ISSCC, 2004.
2. J. Sauerbrey, D. Schmitt-Landsiedel, R. Thewes, "A 0.5-V 1-μ W Successive Approximation ADC", IEEE JSSC, 38(7), July 2003.
3. D. Draxelmayr, "A 6b 600MHz 10mW ADC Array in Digital 90nm CMOS", Proc. of IEEE ISSCC, 2004.
4. B.P. Ginsburg, A.P. Chandrakasan, "Dual Scalable 500MS/S, 5b Time-Interleaved SAR ADCs for UWB applications", Proc. of IEEE CICC, 2005.
5. P. Figureido et al., "A 90nm CMOS 1.2V 6b 1GS/s Two-Step Subranging ADC", Proc. of IEEE ISSCC, 2006.
6. Y.D. Jeon et al. "Acquisition-Time Minimization and Merged-Capacitor Switching Techniques for Sampling-Rate and Resolution Improvement of CMOS ADCs", Proc. of IEEE ISCAS, May 2000.
7. T. O. Anderson, "Optimum Control Logic for Successive Approximation Analog-to-Digital Converters", JPL Technical Report, 32-1526, vol. XIII.