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Volumn , Issue , 2009, Pages 111-116

A 20MS/s 5.6 mW 6b asynchronous ADC in 0.6μm CMOS

Author keywords

[No Author keywords available]

Indexed keywords

CONVERSION CYCLES; HIGH-SPEED APPLICATIONS; LOW-POWER; POWER CONSUMPTION; REDUCING POWER; SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTERS;

EID: 62949216429     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSI.Design.2009.56     Document Type: Conference Paper
Times cited : (6)

References (16)
  • 1
    • 33845655208 scopus 로고    scopus 로고
    • A 6-bit 600-ms/s 5.3- mw asynchronous adc in 0.13-μm cmos
    • December
    • S.-W. M. Chen and R. W. Brodersen. A 6-bit 600-ms/s 5.3- mw asynchronous adc in 0.13-μm cmos. IEEE Journal of Solid-State Circuits, 41(12):2669-2680, December 2006.
    • (2006) IEEE Journal of Solid-State Circuits , vol.41 , Issue.12 , pp. 2669-2680
    • Chen, S.-W.M.1    Brodersen, R.W.2
  • 10
    • 33947364789 scopus 로고    scopus 로고
    • An analysis of latch comparator offset due to load capacitor mismatch
    • A. Nikoozadeh and B. Murmann. An analysis of latch comparator offset due to load capacitor mismatch. IEEE Transactions on Circuits and Systems II, 53(12):1398-1402, 2006.
    • (2006) IEEE Transactions on Circuits and Systems II , vol.53 , Issue.12 , pp. 1398-1402
    • Nikoozadeh, A.1    Murmann, B.2
  • 11
    • 0027576335 scopus 로고
    • A current-controlled latch sense amplifier and a static powersaving input buffer for low-power architecture
    • April
    • T. Kobayashi, K. Nogami, T. Shirotori, and Y. Fujimoto. A current-controlled latch sense amplifier and a static powersaving input buffer for low-power architecture. IEEE Journal of Solid-State Circuits, 28(4):523-527, April 1993.
    • (1993) IEEE Journal of Solid-State Circuits , vol.28 , Issue.4 , pp. 523-527
    • Kobayashi, T.1    Nogami, K.2    Shirotori, T.3    Fujimoto, Y.4
  • 12
  • 13
    • 0017980602 scopus 로고
    • A high-speed 8 bit a/d converter based on a gray-code multiple folding circuit
    • June
    • U. Fiedler and D. Seitzer. A high-speed 8 bit a/d converter based on a gray-code multiple folding circuit. IEEE Journal of Solid-State Circuits, SC-14(3):547-552, June 1979.
    • (1979) IEEE Journal of Solid-State Circuits , vol.SC-14 , Issue.3 , pp. 547-552
    • Fiedler, U.1    Seitzer, D.2
  • 15
    • 0016620207 scopus 로고    scopus 로고
    • J. McCreary and P. Gray. All-mos charge redistribution analog-to-digital conversion techniques. i. Solid-State Circuits, IEEE Journal of, 10(6):371-379, Dec 1975.
    • J. McCreary and P. Gray. All-mos charge redistribution analog-to-digital conversion techniques. i. Solid-State Circuits, IEEE Journal of, 10(6):371-379, Dec 1975.
  • 16
    • 0018504891 scopus 로고
    • A two-stage weighted capacitor network for d/a-a/d conversion
    • Aug
    • Y. Yee, L. Terman, and L. Heller. A two-stage weighted capacitor network for d/a-a/d conversion. IEEE Journal of Solid-State Circuits, 14(4):778-781, Aug 1979.
    • (1979) IEEE Journal of Solid-State Circuits , vol.14 , Issue.4 , pp. 778-781
    • Yee, Y.1    Terman, L.2    Heller, L.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.