Forwardflow: A scalable core for power-constrained CMPs

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2010, Pages 14-25

  Gibson, Dan ^a   Wood, David A ^a  

^a University of Wisconsin Madison   (United States)

Author keywords

Chip Multiprocessor (CMP); Power; Scalable core

Indexed keywords

ARCHITECTURAL LEVELS; BEST MATCH; CHIP MULTIPROCESSOR; CHIP MULTIPROCESSORS; COMMODITIZATION; COMMODITY HARDWARE; CURRENT TRENDS; DATAFLOW; INSTRUCTION LEVEL PARALLELISM; INSTRUCTION SET ARCHITECTURE; MULTIPLE THREADS; MULTITHREADED; PARALLEL SOFTWARE; PERFORMANCE GAIN; POWER CONSUMPTION; POWER LIMITATIONS; POWER SCALABLE; RUNTIMES; SYSTEM SOFTWARES; THREAD LEVEL PARALLELISM;

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; SYSTEMS ANALYSIS;

COMPUTER SOFTWARE;

EID: 77955010938     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1815961.1815966     Document Type: Conference Paper

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