Energy-efficient hybrid wakeup logic

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 196-201

  Huang, Michael ^a   Renau, Jose ^a   Torrellas, Josep ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

Issue logic; Low power; Wakeup logic

Indexed keywords

COMPARATOR CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY CONSERVATION; MICROCOMPUTERS; MULTIMEDIA SYSTEMS; OPTIMIZATION; PROGRAM COMPILERS;

ISSUE LOGIC; LOW POWER; WAKEUP LOGIC;

COMPUTER ARCHITECTURE;

EID: 0036949790     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/lpe.2002.146736     Document Type: Conference Paper

References (14)

1. R. Bahar and S. Manne. Power and Energy Reduction Via Pipeline Balancing. In International Symposium on Computer Architecture, pages 218-229, May 2001.
2. M. Brown, J. Stark, and Y. Patt. Select-Free Instruction Scheduling Logic. In International Symposium on Microarchitecture, pages 204-213, Dec. 2001.
3. R. Canal and A. Gonzalez. A Low-Complexity Issue Logic. In International Conference on Supercomputing, pages 327-335, June 2000.
4. J. Farrell and T. Fischer. Issue Logic for a 600-MHz Out-of-Order Execution Microprocessor. IEEE Journal of Solid-State Circuits, 33(5):707-712, May 1996.
5. D. Folegnani and A. Gonzalez. Energy-Effective Issue Logic. In International Symposium on Computer Architecture, pages 230-239, May 2001.
6. K. Ghose. Reducing Energy Requirements for Instruction Issue and Dispatch in Superscalar Microprocessors. In International Symposium on Low Power Electronics and Design, pages 231-233, Aug. 2000.
7. M. Goshima, K. Nishino, Y. Nakashima, S. Mori, T. Kitamura, and S. Tomita. A High-Speed Dynamic Instruction Scheduling Scheme for Superscalar Processors. In International Symposium on Microarchitecture, pages 225-236, Dec. 2001.
8. V. Krishnan and J. Torrellas. A Direct Execution Framework for Fast and Accurate Simulation of Superscalar Processors. In International Conference on Parallel Architectures and Compilation Techniques, pages 286-293, Oct. 1998.
9. S. Onder and R. Gupta. Superscalar Execution With Dynamic Data Forwarding. In International Conference on Parallel Architectures and Compilation Techniques, pages 130-135, Oct. 1998.
10. S. Palacharla, N. Jouppi, and J. Smith. Complexity Effective Superscalar Processors. In International Symposium on Computer Architecture, pages 206-218, June 1997.
11. D. Ponomarev, G. Kucuk, and K. Ghose. Reducing Power Requirements of Instruction Scheduling Through Dynamic Allocation of Multiple Datapath Resources. In International Symposium on Microarchitecture, pages 90-101, Dec. 2001.
12. S. Weiss and J. Smith. Instruction Issue Logic in Pipelined Supercomputers. IEEE Transactions on Computers, 33(11):1013-1022, Nov. 1984.
13. K. Yeager. The MIPS R10000 Superscalar Microprocessor. IEEE Micro, 16(2):28-41, Apr. 1996.
14. V. Zyuban and P. Kogge. Optimization of High-Performance Superscalar Architectures for Energy Efficiency. In International Symposium on Low Power Electronics and Design, pages 84-89, Aug. 2000.