Direct instruction wakeup for out-of-order processors

Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems

Volumn , Issue , 2004, Pages 2-9

  Ramírez, Marco A ^a,d   Cristal, Adrian ^a   Veidenbaum, Alexander V ^b   Villa, Luis ^c,d   Valero, Mateo ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b Irvine   (United States)

^c INSTITUTO MEXICANO DEL PETRÓLEO   (Mexico)

^d INSTITUTO POLITÉCNICO NACIONAL   (Mexico)

Author keywords

CAM; Direct Wakeup; Issue Queue; Low Power; Out of Order Processors; Wakeup Instructions

Indexed keywords

CAPACITANCE; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; ENERGY DISSIPATION; ENERGY UTILIZATION; OPTIMIZATION;

DIRECT WAKEUP; ISSUE QUEUE; LOW-POWER; OUT-OF-ORDER PROCESSORS; WAKEUP INSTRUCTIONS;

PROGRAM PROCESSORS;

EID: 17444373938     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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