A scalable low power issue queue for large instruction window processors

Proceedings of the International Conference on Supercomputing

Volumn , Issue , 2006, Pages 167-176

  Vivekanandham, Rajesh ^a   Amrutur, Bharadwaj ^a   Govindarajan, R ^a  

^a INDIAN INSTITUTE OF SCIENCE   (India)

Author keywords

Complexity effective architecture; Issue logic; Low power architecture; Wakeup logic

Indexed keywords

COMPUTER RESOURCE MANAGEMENT; ENERGY EFFICIENCY; INDEXING (OF INFORMATION); PARALLEL PROCESSING SYSTEMS; PROBLEM SOLVING; QUEUEING NETWORKS; RESPONSE TIME (COMPUTER SYSTEMS);

COMPLEXITY EFFECTIVE ARCHITECTURE; ISSUE LOGIC; LOW POWER ARCHITECTURE; WAKEUP LOGIC;

PROGRAM PROCESSORS;

EID: 34547416583     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1183401.1183427     Document Type: Conference Paper

References (26)

1. V. Agarwal, M. Hrishikesh, S. Keckler, and D. Burger. Clock rate versus IPC: The end of the road for conventional microarchitectures. In Proceedings of the 27th Annual International Symposium on Computer Architecture, 2000.
2. H. Akkary, R. Rajwar, and S. T. Srinivasan. Checkpoint processing and recovery: Towards scalable large instruction window processors. In Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003.
3. M. Brown, J. Stark, and Y. Patt. Select-free instruction scheduling logic. In Proceedings of 34th International Symposium on Microarchitecture, 2001.
4. D. C. Burger and T. M. Austin. The Simplescalar tool set, version 2.0. Technical Report CS-TR-97-1342, University of Wisconsin, Madison, 1997.
5. A. Buyuktosunoglu and D. H. Albonesi. Tradeoffs in power-efficient issue queue design. In Proceedings of the International Symposium on Low Power Electronics and Design, 2002.
6. A. Cristal, D. Ortega, J. Llosa, and M. Valero. Kilo-instruction processors. ACM Transactions on Architecture and Code Optimization, 1(4), 2004.
7. D.Ernst, A.Hamel, and T.Austin. Cyclone: a broadcast-free dynamic instruction scheduler selective replay. In Proceedings of the 30th Annual International Symposium on Computer Architecture, 2003.
8. D. Ernst and T. M. Austin. Efficient dynamic scheduling through tag elimination. In Proceedings of 29th International Symposium on Computer Architecture, 2002.
9. R. Gonzalez and M. Horowitz. Energy dissipation in general purpose microprocessors. In IEEE Journal of Solid-State Circuits, 1996.
10. M. Goshima, K. Nishino, Y. Nakashima, S. Mori, T. Kitamura, and S. Tomita. A high-speed dynamic instruction scheduling scheme for superscalar processors. In Proceedings of the 34th International Symposium on Microarchitecture, 2001.
11. M. Hrishikesh, N. P. Jouppi, K. I. Farkas, D. Burger, , and S. W. K. P. Shivakumar. The optimal useful logic depth per pipeline stages is 6-8 fo4. In Proceedings of 29th International Symposium on Computer Architecture, 2002.
12. J. S. Hu, N. Vijaykrishnan, and M. J. Irwin. Exploring wakeup-free instruction scheduling. In Proceedings of the 10th International Symposium on High Performance Computer Architecture, 2004.
13. M. Huang, J. Renau, and J. Torellas. Energy-efficient hybrid wakeup logic. In Proceedings of the International Symposium on Low Power Electronics and Design, 2002.
14. C. N. Keltcher, K. J. McGrath, A. Ahmed, and P. Conway. The AMD Opteron processor for multiprocessor servers. IEEE Micro, 23(2), 2003.
15. I. Kim and M. Lipasti. Half price architecture. In Proceedings of the 30th International Symposium on Microarchitecture, 2003.
16. A. KleinOsowski, J. Flynn, N. Meares, and D. J. Lilja. Adapting the SPEC2000 benchmarks suite for simulation-based computer architecture research. In Workshop on Workload Characterization in International Conference on Computer Design, 2000.
17. P. Michaud and A. Seznec. Data-flow prescheduling for large instruction windows in out-of-order processors. In Proceedings of 7th International Symposium on High Performance Computer Architecture, 2001.
18. Mosis.org. www.mosis.org/cgi-bin/cgiwrap/umosis/swp/params/ibm-013/t4bj- params.txt.
19. S. Palacharla, N. P. Jouppi, and J. E. Smith. Complexity-effective superscalar processors. In Proceedings of 24th International Symposium on Computer Architecture, 1997.
20. T. Sato, Y. Nakamura, and I. Arita. Revisiting direct tag search algorithm on superscalar processors. In Workshop on Complexity-Effective Design held in conjunction with the 28th Annual International Symposium on Computer Architecture, 2004.
21. T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically characterizing large scale program behavior. In Proceedings of the 10th International Conference on Architectural Support for Programming, 2002.
22. P. Shivakumar and N. P. Jouppi. Cacti 3.0: An integrated cache timing, power, and area model. Technical report, Western Research Laboratory, Compaq Computer Corporation, 2001.
23. J. Stark, M. Brown, and Y. Patt. On pipelining dynamic instruction scheduling logic. In Proceedings of the 33rd International Symposium on Microarchitecture, 2000.
24. R. Vivekanandham, B. Amrutur, and R. Govindarajan. A scalable low power issue queue for large instruction window processors. Technical Report TR-LHPC-01-2006, HPC, SERC, Indian Institute of Science, 2005.
25. D. Wall. Limits of instruction-level parallelism. Technical report, Western Research Laboratory, Compaq Computer Corporation, 1993.
26. N. Weste and D. Harris. CMOS VLSI Design : A Circuits and Systems Perspective, 3rd edition. Addison-Wesley Publishing Company, 2005.