Robust energy-efficient adder topologies

Proceedings - Symposium on Computer Arithmetic

Volumn , Issue , 2007, Pages 16-25

  Patil, Dinesh ^a   Azizi, Omid ^a   Horowitz, Mark ^a   Ron, Ho ^b   Ananthraman, Rajesh ^c  

^a STANFORD UNIVERSITY   (United States)

^b SUN MICROSYSTEMS   (United States)

^c NVIDIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDER TOPOLOGY; ENERGY-DELAY TRADEOFF CURVES; LOGIC STAGES;

ENERGY DISSIPATION; ENERGY EFFICIENCY; ROBUST CONTROL; THRESHOLD VOLTAGE; TOPOLOGY; TRANSISTORS;

ADDERS;

EID: 36049008846     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ARITH.2007.31     Document Type: Conference Paper

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