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Volumn , Issue , 2007, Pages 275-280

Multi-dimensional circuit and micro-architecture level optimization

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY CONSERVATION; LOGIC DESIGN; OPTIMIZATION; PROBLEM SOLVING; SENSITIVITY ANALYSIS;

EID: 34548125229     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2007.105     Document Type: Conference Paper
Times cited : (5)

References (18)
  • 5
    • 34548119941 scopus 로고    scopus 로고
    • Hierarchical power-performance optimization of digital filters for universal radio
    • S. Farhana, L. Melinda, and N. Borivoje. Hierarchical power-performance optimization of digital filters for universal radio. In SRC Student Symposium, 2006.
    • (2006) SRC Student Symposium
    • Farhana, S.1    Melinda, L.2    Borivoje, N.3
  • 7
    • 33847708700 scopus 로고    scopus 로고
    • M. Horowitz, E. Alon, D. Patil, S. Naffziger, R. Kumar, and K. Bernstein. Scaling, power, and the future of cmos. In IEEE International Electron Devices Meeting, page keynode talk, 2005.
    • M. Horowitz, E. Alon, D. Patil, S. Naffziger, R. Kumar, and K. Bernstein. Scaling, power, and the future of cmos. In IEEE International Electron Devices Meeting, page keynode talk, 2005.
  • 12
    • 0043136424 scopus 로고    scopus 로고
    • Performance trade-off analysis of analog circuits by normal-boundary intersection
    • G. Stehr, H. Graeb, and K. Antreich. Performance trade-off analysis of analog circuits by normal-boundary intersection. In Proc. Design Automation Conf (DAC), pages 958-963, 2003.
    • (2003) Proc. Design Automation Conf (DAC) , pp. 958-963
    • Stehr, G.1    Graeb, H.2    Antreich, K.3
  • 17
    • 0036953966 scopus 로고    scopus 로고
    • Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels
    • V. Zyuban and R N. Strenski. Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels. In Proc. Int. Symp. on Low Power Electronics and Design(ISLPED), pages 166-171, 2002.
    • (2002) Proc. Int. Symp. on Low Power Electronics and Design(ISLPED) , pp. 166-171
    • Zyuban, V.1    Strenski, R.N.2
  • 18
    • 0348017034 scopus 로고    scopus 로고
    • Balancing hardware intensity in microprocessor pipelines
    • V. Zyuban and R N. Strenski. Balancing hardware intensity in microprocessor pipelines. IBM J. Res. & Dev., 47:585-598, 2003.
    • (2003) IBM J. Res. & Dev , vol.47 , pp. 585-598
    • Zyuban, V.1    Strenski, R.N.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.