-
1
-
-
0033717865
-
Clock rate versus IPC: The end of the road for conventional microarchitectures
-
(Vancouver, B.C., Canada, June 2000). ACM Press, New York
-
Agarwal, V., Hrishkesh, M. S., Keckler, S. W., and Burger, D. 2000. Clock rate versus IPC: The end of the road for conventional microarchitectures. In Proceedings of the 27th Annual International Symposium on Computer Architectures (Vancouver, B.C., Canada, June 2000). ACM Press, New York, 248-259.
-
(2000)
Proceedings of the 27th Annual International Symposium on Computer Architectures
, pp. 248-259
-
-
Agarwal, V.1
Hrishkesh, M.S.2
Keckler, S.W.3
Burger, D.4
-
2
-
-
0034316092
-
Power-aware microarchitecture: design and modeling challenges for the next-generation microprocessors
-
Brooks, D., Bose, P., Schuster, S. E., Jacobson, H., Kudva, P. N., Buyuktosunoglu, A., Wellman, J. D., Zyuban, V., Gupta, M., and Cook, P. W. 2000. Power-aware microarchitecture: design and modeling challenges for the next-generation microprocessors. IEEE Micro 20 (2000), 26-44.
-
(2000)
IEEE Micro
, vol.20
, pp. 26-44
-
-
Brooks, D.1
Bose, P.2
Schuster, S.E.3
Jacobson, H.4
Kudva, P.N.5
Buyuktosunoglu, A.6
Wellman, J.D.7
Zyuban, V.8
Gupta, M.9
Cook, P.W.10
-
4
-
-
0023386285
-
Characterization of branch and data dependencies in programs for evaluating pipeline performance
-
Emma, P. G. and Davidson, E. S. 1987. Characterization of branch and data dependencies in programs for evaluating pipeline performance. IEEE Trans. Computers C-36 (1987), 859-875.
-
(1987)
IEEE Trans. Computers
, vol.C-36
, pp. 859-875
-
-
Emma, P.G.1
Davidson, E.S.2
-
5
-
-
0032592098
-
Deep-submicron microprocessor design issues
-
Flynn, M. J., Hung, P., and Rudd, K. 1999. Deep-submicron microprocessor design issues. IEEE Micro 19 (1999), 11-22.
-
(1999)
IEEE Micro
, vol.19
, pp. 11-22
-
-
Flynn, M.J.1
Hung, P.2
Rudd, K.3
-
6
-
-
0030243819
-
Energy dissipation in general purpose processors
-
González, R. and Horowitz, M. 1996. Energy dissipation in general purpose processors. IEEE J. Solid-State Circuits 31 (1996), 1277-1284.
-
(1996)
IEEE J. Solid-State Circuits
, vol.31
, pp. 1277-1284
-
-
González, R.1
Horowitz, M.2
-
7
-
-
0036296817
-
The optimum pipeline depth for a microprocessor
-
(Anchorage, AL, May 2002). IEEE Computer Society, Washington DC
-
Hartstein, A. and Puzak, T. R. 2002. The optimum pipeline depth for a microprocessor. In Proceedings of the 29th Annual International Symposium on Computer Architectures (Anchorage, AL, May 2002). IEEE Computer Society, Washington DC, 7-13.
-
(2002)
Proceedings of the 29th Annual International Symposium on Computer Architectures
, pp. 7-13
-
-
Hartstein, A.1
Puzak, T.R.2
-
8
-
-
16244388785
-
Optimum power/performance pipeline depth
-
(San Diego, CA, Dec. 2003). IEEE Computer Society Press, Los Alamitos, CA
-
Hartstein, A. and Puzak, T. R. 2003. Optimum power/performance pipeline depth. In Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture (San Diego, CA, Dec. 2003). IEEE Computer Society Press, Los Alamitos, CA, 117-125.
-
(2003)
Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture
, pp. 117-125
-
-
Hartstein, A.1
Puzak, T.R.2
-
9
-
-
0036287089
-
The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays
-
(Anchorage, AL, May 2002). IEEE Computer Society, Washington, DC
-
Hrishkesh, M., Jouppi, N., Farkas, K., Burger, D., Keckler, S., and Shivakumar, P. 2002. The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays. In Proceedings of the 29th Annual Int. Symposium on Computer Architectures (Anchorage, AL, May 2002). IEEE Computer Society, Washington, DC, 14-24.
-
(2002)
Proceedings of the 29th Annual Int. Symposium on Computer Architectures
, pp. 14-24
-
-
Hrishkesh, M.1
Jouppi, N.2
Farkas, K.3
Burger, D.4
Keckler, S.5
Shivakumar, P.6
-
10
-
-
0022584417
-
Optimal pipelining in supercomputers
-
(Tokyo, June 1986). IEEE Computer Society, Washington, DC
-
Kunkel, S. r. And Smith, J. E. 1986. Optimal pipelining in supercomputers. In Proceedings of the 13th Annual International Symposium on Computer Architectures (Tokyo, June 1986). IEEE Computer Society, Washington, DC, 404-411.
-
(1986)
Proceedings of the 13th Annual International Symposium on Computer Architectures
, pp. 404-411
-
-
Kunkel, S.r.1
Smith, J.E.2
-
11
-
-
0036296819
-
Increasing processor performance by implementing deeper pipelines
-
(Anchorage, Alaska, May 2002). IEEE Computer Society, Washington, DC
-
Sprangle, E. and Carmean, D. 2002. Increasing processor performance by implementing deeper pipelines. In Proceedings of the 29th Annual International Symposium on Computer Architectures (Anchorage, Alaska, May 2002). IEEE Computer Society, Washington, DC, 25-35.
-
(2002)
Proceedings of the 29th Annual International Symposium on Computer Architectures
, pp. 25-35
-
-
Sprangle, E.1
Carmean, D.2
-
12
-
-
84948974161
-
Optimizing pipelines for power and performance
-
(Istanbul, Nov. 2002). IEEE Computer Society Press, Los Alamitos, CA
-
Srinivasan, V., Brooks, D., Gschwind, M., Bose, P., Zyuban, V., Strenski, P. N., and Emma, P. G. 2002. Optimizing pipelines for power and performance. In Proceedings of the 35th Annual IEEE/ACM International Symposium on Microarchitecture (Istanbul, Nov. 2002). IEEE Computer Society Press, Los Alamitos, CA, 333-344.
-
(2002)
Proceedings of the 35th Annual IEEE/ACM International Symposium on Microarchitecture
, pp. 333-344
-
-
Srinivasan, V.1
Brooks, D.2
Gschwind, M.3
Bose, P.4
Zyuban, V.5
Strenski, P.N.6
Emma, P.G.7
-
13
-
-
0036953966
-
Unified methodology for resolving power-performance tradeoffs of the microarchitectural and circuit levels
-
(Monterey, CA, Aug. 2002). ACM Press, New York
-
Zyuban, V. and Strenski, P. 2002. Unified methodology for resolving power-performance tradeoffs of the microarchitectural and circuit levels. In Proceedings of the International Symposium on Low-Power Electronics and Design (Monterey, CA, Aug. 2002). ACM Press, New York, 166-171.
-
(2002)
Proceedings of the International Symposium on Low-Power Electronics and Design
, pp. 166-171
-
-
Zyuban, V.1
Strenski, P.2
|