An integrated framework for joint design space exploration of microarchitecture and circuits

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2010, Pages 250-255

  Azizi, Omid ^a   Mahesri, Aqeel ^b   Stevenson, John P ^a   Patel, Sanjay J ^c   Horowitz, Mark ^a  

^a Stanford University   (United States)

^b NVIDIA   (United States)

^c University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONVEX OPTIMIZATION; ELECTRIC NETWORK ANALYSIS; ENERGY EFFICIENCY; INTEGRATED CIRCUIT MANUFACTURE; TIMING CIRCUITS;

ARCHITECTURAL MODELS; ARCHITECTURAL TRADEOFFS; CIRCUIT ARCHITECTURES; INTEGRATED FRAMEWORKS; JOINT OPTIMIZATION; MICRO ARCHITECTURES; OUT-OF-ORDER PROCESSORS; STATISTICAL INFERENCE;

ARCHITECTURAL DESIGN;

EID: 77953118550     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2010.5457204     Document Type: Conference Paper

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