메뉴 건너뛰기




Volumn 6, Issue 1, 2010, Pages 218-226

Low-power soft error hardened latch

Author keywords

Alpha particles; Atmospheric neutrons; Design for reliability; Design for soft error mitigation; Fault tolerant design; Hardened latch; Reliability; Single Event transients; Single Event upsets; Soft errors; Static latch

Indexed keywords

ALPHA PARTICLES; COMPUTER CIRCUITS; ERROR CORRECTION; HARDENING; LOGIC CIRCUITS; RADIATION HARDENING; RELIABILITY; SPICE; TRANSIENTS; TRIGGER CIRCUITS;

EID: 77954944905     PISSN: 15461998     EISSN: 15462005     Source Type: Journal    
DOI: 10.1166/jolpe.2010.1073     Document Type: Conference Paper
Times cited : (21)

References (27)
  • 5
    • 34548206267 scopus 로고    scopus 로고
    • Latch susceptibility to transient faults and new hardening approach
    • M. Omana, D. Rossi, and C. Metra, Latch susceptibility to transient faults and new hardening approach. IEEE Transactions on Computers 56, 1255 (2007).
    • (2007) IEEE Transactions on Computers , vol.56 , pp. 1255
    • Omana, M.1    Rossi, D.2    Metra, C.3
  • 10
    • 64549144240 scopus 로고    scopus 로고
    • Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies
    • M. Fazeli, S. G. Miremadi, A. Ejlali, and A. Patooghy, Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies. IET Computers and Digital Techniques 3, 289 (2009).
    • (2009) IET Computers and Digital Techniques , vol.3 , pp. 289
    • Fazeli, M.1    Miremadi, S.G.2    Ejlali, A.3    Patooghy, A.4
  • 12
    • 0030375853 scopus 로고    scopus 로고
    • Upset hardened memory design for submicron CMOS technology
    • T. Calin, M. Nicolaidis, and R. Velazco, Upset hardened memory design for submicron CMOS technology. IEEE Trans. Nucl. Sci. 43, 2874 (1996).
    • (1996) IEEE Trans. Nucl. Sci. , vol.43 , pp. 2874
    • Calin, T.1    Nicolaidis, M.2    Velazco, R.3
  • 14
    • 40949091053 scopus 로고    scopus 로고
    • Circuit and latch capable of masking soft errors with Schmitt trigger
    • Y. Sasaki, K. Namba, and H. Ito, Circuit and latch capable of masking soft errors with Schmitt trigger. J. Electron. Test. 24, 11 (2008).
    • (2008) J. Electron. Test. , vol.24 , pp. 11
    • Sasaki, Y.1    Namba, K.2    Ito, H.3
  • 17
    • 0346267659 scopus 로고    scopus 로고
    • Clocking and clocked storage elements in a multi-gigahertz environment
    • V. G. Oklobdzija, Clocking and clocked storage elements in a multi-gigahertz environment. IBM Journal of Research and Development 47, 567 (2003).
    • (2003) IBM Journal of Research and Development , vol.47 , pp. 567
    • Oklobdzija, V.G.1
  • 18
    • 38749112453 scopus 로고    scopus 로고
    • Use of pass transistor logic to minimize the impact of soft errors in combinational circuits
    • J. Kumar and M. B. Tahoori, Use of pass transistor logic to minimize the impact of soft errors in combinational circuits. Workshop on System Effects of Logic Soft Errors (SELSE) (2005), pp. 67-74.
    • (2005) Workshop on System Effects of Logic Soft Errors (SELSE) , pp. 67-74
    • Kumar, J.1    Tahoori, M.B.2
  • 21
    • 15044363155 scopus 로고    scopus 로고
    • Robust system design with built-in soft-error resilience
    • S. Mitra, N. Seifert, M. Zhang, Q. Shi, and K. S. Kim, Robust system design with built-in soft-error resilience. IEEE Computer 38, 43 (2005).
    • (2005) IEEE Computer , vol.38 , pp. 43
    • Mitra, S.1    Seifert, N.2    Zhang, M.3    Shi, Q.4    Kim, K.S.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.