Enhancing debugging of multiple missing control errors in reversible logic

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2010, Pages 465-470

  Jung, Jean Christoph ^a   Frehse, Stefan ^a   Wille, Robert ^a   Drechsler, Rolf ^a  

^a UNIVERSITY OF BREMEN   (Germany)

Author keywords

boolean satisfiablity (SAT); debugging; reversible logic

Indexed keywords

ALTERNATIVE METHODS; CONTROL ERRORS; DESIGN FLOWS; ERROR LOCATION; ERROR MODEL; HARDWARE TECHNOLOGY; REVERSIBLE CIRCUITS; REVERSIBLE LOGIC; RUNTIMES;

ERRORS; LAKES; LOGIC GATES;

LOGIC CIRCUITS;

EID: 77954526050     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1785481.1785588     Document Type: Conference Paper

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