-
2
-
-
34547476643
-
PicoServer: Using 3D Stacking Technology to Enable a Compact Energy Efficient Chip Multiprocessor
-
T. Kgil, S. D'Souza, A. Saidi, N. Binkert, R. Dreslinski, T. Mudge, S. Reinhardt, K. Flautner, "PicoServer: Using 3D Stacking Technology to Enable a Compact Energy Efficient Chip Multiprocessor," The 12th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 117-128, 2006.
-
(2006)
The 12th International Conference on Architectural Support for Programming Languages and Operating Systems
, pp. 117-128
-
-
Kgil, T.1
D'Souza, S.2
Saidi, A.3
Binkert, N.4
Dreslinski, R.5
Mudge, T.6
Reinhardt, S.7
Flautner, K.8
-
3
-
-
51949114502
-
Two-bit cell operations in diode-switch phase change memory cells with 90nm technology
-
D.H. Kang, et al., "Two-bit Cell Operations in Diode-Switch Phase Change Memory Cells with 90nm Technology," IEEE symposium on VLSI Technology Digest of Technical Papers, pages 98-99, 2008.
-
(2008)
IEEE Symposium on VLSI Technology Digest of Technical Papers
, pp. 98-99
-
-
Kang, D.H.1
-
4
-
-
70450235471
-
Architecting phase change memory as a scalable DRAM alternative
-
B. Lee, E. Ipek, O. Mutlu, and D. Burger, "Architecting Phase Change Memory as a Scalable DRAM Alternative," The 36th International Symposium on Computer Architecture (ISCA), pages 2-13, 2009.
-
(2009)
The 36th International Symposium on Computer Architecture (ISCA)
, pp. 2-13
-
-
Lee, B.1
Ipek, E.2
Mutlu, O.3
Burger, D.4
-
5
-
-
0346750534
-
Energy management for commercial servers
-
C. Lefurgy, K. Rajamani, F. Rawson, W. Felter, M. Kistler, and T.W. Keller, "Energy Management for Commercial Servers," IEEE Computer, Vol.36(12):39-48, 2003.
-
(2003)
IEEE Computer
, vol.36
, Issue.12
, pp. 39-48
-
-
Lefurgy, C.1
Rajamani, K.2
Rawson, F.3
Felter, W.4
Kistler, M.5
Keller, T.W.6
-
6
-
-
28344453642
-
Bridging the processor-memory performance Gap with 3D IC technology
-
C.C. Liu, I. Ganusov, M. Burtscher, S. Tiwari, "Bridging the Processor-Memory Performance Gap with 3D IC Technology," IEEE Design and Test of Computers, Vol.22(6):556-564, 2005.
-
(2005)
IEEE Design and Test of Computers
, vol.22
, Issue.6
, pp. 556-564
-
-
Liu, C.C.1
Ganusov, I.2
Burtscher, M.3
Tiwari, S.4
-
7
-
-
33748870886
-
Multifacet's General Execution-driven Multiprocessor Simulator (GEMS) toolset
-
M.M. Martin, D. J. Sorin, B.M. Beckmann, M.R. Marty, M. Xu, A.R. Alameldeen, K.E. Moore, M.D. Hill, and D.A. Wood, "Multifacet's General Execution-driven Multiprocessor Simulator (GEMS) Toolset," Computer Architecture News, pages 92-99, 2005.
-
(2005)
Computer Architecture News
, pp. 92-99
-
-
Martin, M.M.1
Sorin, D.J.2
Beckmann, B.M.3
Marty, M.R.4
Xu, M.5
Alameldeen, A.R.6
Moore, K.E.7
Hill, M.D.8
Wood, D.A.9
-
8
-
-
84946099927
-
Beyond performance: Secure and fair memory management for multiple systems on a chip
-
C. Macian, S. Dharmapurikar, and J. Lockwood, "Beyond Performance: Secure and Fair Memory Management for Multiple Systems on a Chip," IEEE International Conference on Field- Programmable Technology (FPT), pages 348-351, 2003.
-
(2003)
IEEE International Conference on Field-Programmable Technology (FPT)
, pp. 348-351
-
-
MacIan, C.1
Dharmapurikar, S.2
Lockwood, J.3
-
9
-
-
0036469676
-
Simics: A full system simulation platform
-
P. S. Magnusson, et al., "Simics: A full system simulation platform," IEEE Computer, Vol.35(2):50-58, 2002.
-
(2002)
IEEE Computer
, vol.35
, Issue.2
, pp. 50-58
-
-
Magnusson, P.S.1
-
11
-
-
77954026859
-
-
Micron. 1Gb DDR2 SDRAM Component: MT47H128M8HQ-25, May
-
Micron. 1Gb DDR2 SDRAM Component: MT47H128M8HQ-25, May 2007. http://download.micron.com/pdf/datasheets/dram/ddr2/1GbDDR2.pdf.
-
(2007)
-
-
-
14
-
-
34548050337
-
Fair queuing memory systems
-
K.J. Nesbit, N. Aggarwal, J. Laudon and J.E. Smith, "Fair queuing Memory Systems," The 39th IEEE/ACM International Symposium On Microarchitecture (MICRO), pages 208-222, 2006.
-
(2006)
The 39th IEEE/ACM International Symposium on Microarchitecture (MICRO)
, pp. 208-222
-
-
Nesbit, K.J.1
Aggarwal, N.2
Laudon, J.3
Smith, J.E.4
-
15
-
-
34548042910
-
Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches
-
M.K. Qureshi, and Y.N. Patt, "Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches," The 39th IEEE/ACM International Symposium On Microarchitecture (MICRO), pages 423-1132 2006.
-
(2006)
The 39th IEEE/ACM International Symposium on Microarchitecture (MICRO)
, pp. 423-1132
-
-
Qureshi, M.K.1
Patt, Y.N.2
-
16
-
-
70450273507
-
Scalable high performance main memory system using phase-change memory technology
-
M.K. Qureshi, V. Srinivasan, and J.A. Rivers, "Scalable High Performance Main Memory System Using Phase-Change Memory Technology," The 36th International Symposium on Computer Architecture (ISCA), pages 24-33, 2009.
-
(2009)
The 36th International Symposium on Computer Architecture (ISCA)
, pp. 24-33
-
-
Qureshi, M.K.1
Srinivasan, V.2
Rivers, J.A.3
-
18
-
-
47849130815
-
Effective management of DRAM bandwidth in multicore processors
-
N. Rafique, W.T. Lim, and M. Thottethodi, "Effective Management of DRAM Bandwidth in Multicore Processors," The 16th International Conference on Parallel Architectures and Compilation Techniques (PACT), pages 245-258, 2007.
-
(2007)
The 16th International Conference on Parallel Architectures and Compilation Techniques (PACT)
, pp. 245-258
-
-
Rafique, N.1
Lim, W.T.2
Thottethodi, M.3
-
20
-
-
0033691565
-
Memory access scheduling
-
S. Rixner, W.J. Dally, U.J. Kapasi, P. Mattson, and J.D. Owens, "Memory Access Scheduling," The 27th International Symposium on Computer Architecture (ISCA), pages 128-138, 2000.
-
(2000)
The 27th International Symposium on Computer Architecture (ISCA)
, pp. 128-138
-
-
Rixner, S.1
Dally, W.J.2
Kapasi, U.J.3
Mattson, P.4
Owens, J.D.5
-
21
-
-
77954014320
-
-
http://www.spec.org.
-
-
-
-
22
-
-
0026925878
-
Optimal partitioning of cache memory
-
H.S. Stone, J. Turek, and J.L. Wolf, "Optimal Partitioning of Cache Memory," IEEE Transactions on Computers,Vol. 41(9):1054-1068, 1992.
-
(1992)
IEEE Transactions on Computers
, vol.41
, Issue.9
, pp. 1054-1068
-
-
Stone, H.S.1
Turek, J.2
Wolf, J.L.3
-
23
-
-
84949769332
-
A new memory monitoring scheme for memory aware scheduling and partitioning
-
G.E. Suh, S. Devada, and L. Rudolph, "A New Memory Monitoring Scheme for Memory Aware Scheduling and Partitioning," The 8th International Symposium on High-Performance Computer Architecture (HPCA), pages 117-128, 2002.
-
(2002)
The 8th International Symposium on High-Performance Computer Architecture (HPCA)
, pp. 117-128
-
-
Suh, G.E.1
Devada, S.2
Rudolph, L.3
-
24
-
-
64949106457
-
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
-
G. Sun, X. Dong, Y. Xie, J. Li, and Y. Chen, "A Novel Architecture of the 3D Stacked MRAM L2 Cache for CMPs," The 15th International Symposium on High-Performance Computer Architecture (HPCA), pages 239-249, 2009.
-
(2009)
The 15th International Symposium on High-Performance Computer Architecture (HPCA)
, pp. 239-249
-
-
Sun, G.1
Dong, X.2
Xie, Y.3
Li, J.4
Chen, Y.5
-
25
-
-
52649139073
-
A comprehensive memory modeling tool and its application to the design and analysis of future memory hierarchies
-
S. Thoziyoor, J.H. Ahn, M. Monchiero, J.B. Brockman, and N.P. Jouppi, "A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies," The 35th International Symposium on Computer Architecture (ISCA), pages 51-62, 2008.
-
(2008)
The 35th International Symposium on Computer Architecture (ISCA)
, pp. 51-62
-
-
Thoziyoor, S.1
Ahn, J.H.2
Monchiero, M.3
Brockman, J.B.4
Jouppi, N.P.5
-
26
-
-
0029179077
-
The SPLASH-2 Programs: Characterization and methodological considerations
-
S.C. Woo, M. Ohara, E. Torrie, J.P. Singh, and A. Gupta, "The SPLASH-2 Programs: Characterization and Methodological Considerations," The 22nd International Symposium on Computer Architecture (ISCA), pages 24-36, 1995.
-
(1995)
The 22nd International Symposium on Computer Architecture (ISCA)
, pp. 24-36
-
-
Woo, S.C.1
Ohara, M.2
Torrie, E.3
Singh, J.P.4
Gupta, A.5
-
27
-
-
21244464284
-
5 Confined Structures and Integration of 64Mb Phase-Changed Random Access Memory
-
5 Confined Structures and Integration of 64Mb Phase-Changed Random Access Memory," Japanese Journal of Applied Physics, pages 2691-2695, 2005.
-
(2005)
Japanese Journal of Applied Physics
, pp. 2691-2695
-
-
Yeung, F.1
-
28
-
-
70450277571
-
A durable and energy efficient main memory using phase change memory technology
-
P. Zhou, B. Zhao, J. Yang, and Y. Zhang, "A Durable and Energy Efficient Main Memory Using Phase Change Memory Technology," The 36th International Symposium on Computer Architecture (ISCA), pages 14-23, 2009.
-
(2009)
The 36th International Symposium on Computer Architecture (ISCA)
, pp. 14-23
-
-
Zhou, P.1
Zhao, B.2
Yang, J.3
Zhang, Y.4
|