Development of a numerical model for non-uniformly powered die to improve both thermal and device clock performance

Proceedings of the ASME InterPack Conference 2009, IPACK2009

Volumn 2, Issue , 2010, Pages 111-118

  Karajgikar, Saket ^a   Agonafer, Dereje ^a   Ghose, Kanad ^b   Sammakia, Bahgat ^b   Refai Ahmed, Gamal ^c  

^a UNIVERSITY OF TEXAS AT ARLINGTON   (United States)

^b BINGHAMTON UNIVERSITY   (United States)

^c ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PERFORMANCE; DETRIMENTAL EFFECTS; FUNCTIONAL BLOCK; FUNCTIONAL COMPONENTS; FUNCTIONAL UNITS; HIGH SPEED I/O; HOT SPOT; JUNCTION TEMPERATURES; MAXIMUM TEMPERATURE; MEMORY CONTROLLER; NONUNIFORM; NUMERICAL MODELS; PERFORMANCE LOSS; POWER DISTRIBUTIONS; PRODUCT RELIABILITY; TEMPERATURE GRADIENT; TOTAL POWER;

MICROPROCESSOR CHIPS; MULTIOBJECTIVE OPTIMIZATION;

CACHE MEMORY;

EID: 77953918278     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1115/InterPACK2009-89188     Document Type: Conference Paper

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