Novel thermal validation metrology based on non-uniform power distribution for Pentium® III Xeon™ cartridge processor design with integrated level two cache

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2001, Pages 1181-1186

  Goh, T J ^a   Amir, A N ^a   Chiu, C P ^a   Torresola, J ^a  

^a AMREC   (Malaysia)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER SIMULATION; DESIGN FOR TESTABILITY; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRONICS PACKAGING; FINITE ELEMENT METHOD; HEAT RESISTANCE; INTEGRATED CIRCUIT LAYOUT; INTERFACES (MATERIALS); SILICON WAFERS; SURFACE MOUNT TECHNOLOGY; TEMPERATURE MEASUREMENT;

CARTRIDGE PROCESSOR; MEASUREMENT CAPABILITY ANALYSIS; NON UNIFORM POWER DISTRIBUTION; ORGANIC LAND GRID ARRAY; THERMAL TEST VEHICLE DESIGN; THERMAL VALIDATION METROLOGY;

MICROPROCESSOR CHIPS;

EID: 0034835194     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Pentium ® II processor packaging - Thermal management of SRAM's in a S.E.C. cartridge
2. Application of phase-change materials in pentium ® II and pentium ® II Xeon ™ processor cartridges
3. Product design requirement document - Test vehicle: 2SFTV1