Design rule for minimizing thermal resistance in a non-uniformly powered microprocessor

Annual IEEE Semiconductor Thermal Measurement and Management Symposium

Volumn 2006, Issue , 2006, Pages 108-115

  Kaisare, Abhijit ^a   Agonafer, Dereje ^a   Haji shiekh, A ^a   Chrysler, Greg ^b   Mahajan, Ravi ^b  

^a University of Texas at Arlington   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Non uniform power; Optimization; Thermal resistance

Indexed keywords

CACHE MEMORY; HEAT FLUX; HEAT RESISTANCE; LOGIC DEVICES; OPTIMIZATION; PRODUCT DESIGN;

ELECTRICAL TIMING; EXECUTION TIME; FUNCTIONAL INTEGRATION; NON UNIFORM POWER;

MICROPROCESSOR CHIPS;

EID: 33750097258     PISSN: 10652221     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Abhijit Kaisare,Dereje Agonafer, A. Haji-shiekh, Greg Chrysler and Ravi Mahajan, "Thermal based optimization of functional block distributions in a non-uniformly powered die," published in InterPACK conference,2005.
2. Teck Joo Goh, A.N. Amir, Chia-Pin Chiu and J. Torresola, "Novel thermal validation metrology based on non-uniform power distribution for Pentium(R) III XeonTM cartridge processor design with integrated level two cache,"51st Electronic Components and Technology Conference, 2001, pp. 1181-1186.
3. Teck Joo Goh, "Thermal methodology for evaluating the performance of microelectronic devices with non-uniform power dissipation," 4th Electronics Packaging Technology Conference, 2002. pp. 312-317.
4. V. Gektin, Ron Zhang, M. Vogel, Guoping Xu and M. Lee, "Substantiation of numerical analysis methodology for CPU package with non-uniform heat dissipation and heat sink with simplified fin modeling," Thermal and Thermomechanical Phenomena in Electronic Systems, 2004, pp. 537-542 Vol.1
5. K.K. Sikka, "An analytical temperature prediction method for a chip power map," Semiconductor Thermal Measurement and Management Symposium, 2005, pp. 161-166
6. M.S. June and K.K. Sikka, "Using cap-integral standoffs to reduce chip hot-spot temperatures in electronic packages," Thermal and Thermomechanical Phenomena in Electronic Systems, 2002, pp. 173-178.
7. Zhiping Yu, D. Yergeau, R.W. Dutton, S. Nakagawa and J. Deeney, "Fast placement-dependent full chip thermal simulation," VLSI Technology, Systems, and Applications, 2001, pp. 249-252.
8. Ravi Mahajan, Raj Nair, V. Wakharkar,. " Emerging Directions for packaging technologies," Intel Technology Journal, Q2,2002
9. [S.G. Jagarkal, M.M. Hossain, D. Agonafer, M. Lulu and S. Reh, "Design optimization and reliability of PWB level electronic package," Thermal and Thermomechanical Phenomena in Electronic Systems, 2004, pp. 368-376 Vol.2.
10. Ansys Workbench (9.0) reference manual