A dynamic phase error compensation technique for fast-locking phase-locked loops

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 6, 2010, Pages 1137-1149

  Chiu, Wei Hao ^a   Huang, Yu Hsiang ^a   Lin, Tsung Hsien ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Discriminator aided phase detector (DAPD); Frequency divider; Loop bandwidth; Phase frequency detector (PFD); Phase locked loop (PLL)

Indexed keywords

FREQUENCY DIVIDERS; LOOP BANDWIDTH; PHASE DETECTORS; PHASE FREQUENCY DETECTORS;

ANTENNA PHASED ARRAYS; BANDWIDTH; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; DETECTORS; DISCRIMINATORS; ELECTRIC CHARGE; ERROR COMPENSATION; FREQUENCY DIVIDING CIRCUITS; PUMPS; QUADRATURE AMPLITUDE MODULATION; SIGNAL DETECTION; SPURIOUS SIGNAL NOISE;

PHASE LOCKED LOOPS;

EID: 77953270648     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2046235     Document Type: Article

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