-
1
-
-
9144243660
-
A single-chip digitally calibrated 5.15-5.825-GHz 0.18-μm CMOS transceiver for 802.11 a wireless LAN
-
Dec
-
I. Vassiliou et al., "A single-chip digitally calibrated 5.15-5.825-GHz 0.18-μm CMOS transceiver for 802.11 a wireless LAN," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2221-2231, Dec. 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, Issue.12
, pp. 2221-2231
-
-
Vassiliou, I.1
-
2
-
-
9144232339
-
A 5-GHz direct-conversion CMOS transceiver
-
Dec
-
P. Zhang et al., "A 5-GHz direct-conversion CMOS transceiver," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2232-2238, Dec. 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, Issue.12
, pp. 2232-2238
-
-
Zhang, P.1
-
3
-
-
85016649583
-
A direct-conversion CMOS transceiver for 4.9 - 5.95 GHz multi-standard WLANs
-
T. Maeda et al, "A direct-conversion CMOS transceiver for 4.9 - 5.95 GHz multi-standard WLANs," in IEEE ISSCC Dig. Tech. Papers, 2004, pp. 90-515.
-
(2004)
IEEE ISSCC Dig. Tech. Papers
, pp. 90-515
-
-
Maeda, T.1
-
4
-
-
33947619471
-
A 1 V low-power single-chip CMOS WLAN IEEE 802.1 la transceiver
-
L. Leung, T. Zheng, S. Lou, A. Ng, D. Lau, R. Wang, P. Wu, V. Cheung, G. Wong, and H. C. Luong, "A 1 V low-power single-chip CMOS WLAN IEEE 802.1 la transceiver," in Proc. 32ndEuropean Solid-State Circuits Conf. (ESSCIRC), 2006, pp. 283-286.
-
(2006)
Proc. 32ndEuropean Solid-State Circuits Conf. (ESSCIRC)
, pp. 283-286
-
-
Leung, L.1
Zheng, T.2
Lou, S.3
Ng, A.4
Lau, D.5
Wang, R.6
Wu, P.7
Cheung, V.8
Wong, G.9
Luong, H.C.10
-
5
-
-
0035364272
-
Peak-to-average power ratio in high-order OFDM
-
Jun
-
N. Dinur and D. Wulich, "Peak-to-average power ratio in high-order OFDM," IEEE Trans. Commun., vol. 49, no. 6, pp. 1063-1072, Jun. 2001.
-
(2001)
IEEE Trans. Commun
, vol.49
, Issue.6
, pp. 1063-1072
-
-
Dinur, N.1
Wulich, D.2
-
6
-
-
25444466245
-
Compensation schemes and performance analysis of IQ imbalances in OFDM receivers
-
Aug
-
A. Tarighat, R. Bagheri, and A. H. Sayed, "Compensation schemes and performance analysis of IQ imbalances in OFDM receivers," IEEE Trans. Signal Process., vol. 53, no. 8, pp. 3257-3268, Aug. 2005.
-
(2005)
IEEE Trans. Signal Process
, vol.53
, Issue.8
, pp. 3257-3268
-
-
Tarighat, A.1
Bagheri, R.2
Sayed, A.H.3
-
7
-
-
0036913527
-
A 5 GHz CMOS transceiver for IEEE 802.11a wireless LAN
-
Dec
-
D. Su et al, "A 5 GHz CMOS transceiver for IEEE 802.11a wireless LAN," IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1688-1694, Dec. 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, Issue.12
, pp. 1688-1694
-
-
Su, D.1
-
8
-
-
0035335240
-
A 5.2-GHz CMOS receiver with 62-dB image rejection
-
May
-
B. Razavi, "A 5.2-GHz CMOS receiver with 62-dB image rejection," IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 810-815, May 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, Issue.5
, pp. 810-815
-
-
Razavi, B.1
-
9
-
-
0036540703
-
Design of a low-voltage 5 to 6 GHz voltage controlled oscillator for the 802.11 applications
-
Apr
-
J. R. Anderson, "Design of a low-voltage 5 to 6 GHz voltage controlled oscillator for the 802.11 applications," Appl. Microw. Wireless, Apr. 2002.
-
(2002)
Appl. Microw. Wireless
-
-
Anderson, J.R.1
-
11
-
-
33745155805
-
A 1-V, 9.7 mW CMOS frequency synthesizer for WLAN 802.11a transceivers
-
L. L. K. Leung and H. C. Luong, "A 1-V, 9.7 mW CMOS frequency synthesizer for WLAN 802.11a transceivers," in Symp. VLSI Circuits Dig. Tech. Papers, 2005, pp. 252-255.
-
(2005)
Symp. VLSI Circuits Dig. Tech. Papers
, pp. 252-255
-
-
Leung, L.L.K.1
Luong, H.C.2
-
12
-
-
0032025509
-
A 1.9-GHz silicon receiver with, monolotic image filtering
-
Mar
-
J. Macedo and M. Copeland, "A 1.9-GHz silicon receiver with, monolotic image filtering," IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 378-386, Mar. 1998.
-
(1998)
IEEE J. Solid-State Circuits
, vol.33
, Issue.3
, pp. 378-386
-
-
Macedo, J.1
Copeland, M.2
-
13
-
-
0033902320
-
Current-reuse bleeding mixer
-
Apr
-
S.-G Lee and J.-K. Choi, "Current-reuse bleeding mixer," Electron. Lett., vol. 36, pp. 696-697, Apr. 2000.
-
(2000)
Electron. Lett
, vol.36
, pp. 696-697
-
-
Lee, S.-G.1
Choi, J.-K.2
-
14
-
-
0026835643
-
Design of a bipolar 10-MHz programmable continuous-time 0.05° equiripple linear phase filter
-
Mar
-
Y. De Veirman, "Design of a bipolar 10-MHz programmable continuous-time 0.05° equiripple linear phase filter," IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 324-331, Mar. 1992.
-
(1992)
IEEE J. Solid-State Circuits
, vol.27
, Issue.3
, pp. 324-331
-
-
De Veirman, Y.1
-
15
-
-
8344240468
-
Novel automatic tuning method of RC filters using a digital-DLL technique
-
Nov
-
T. Oshima, K. Maio, W. Hioe, and Y. Shibahara, "Novel automatic tuning method of RC filters using a digital-DLL technique," IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 2052-2054, Nov. 2004.
-
(2004)
IEEE J. Solid-State Circuits
, vol.39
, Issue.11
, pp. 2052-2054
-
-
Oshima, T.1
Maio, K.2
Hioe, W.3
Shibahara, Y.4
-
16
-
-
2442715515
-
A 2 GHz CMOS variable-gain amplifier with 50 dB linear-in-magnitude controlled gain range for 10 GBase-LX4 ethernet
-
C.-H. Wu, C.-S. Liu, and S.-L. Liu, "A 2 GHz CMOS variable-gain amplifier with 50 dB linear-in-magnitude controlled gain range for 10 GBase-LX4 ethernet," in IEEE ISSCC Dig. Tech. Papers, 2004, vol. 1, pp. 484-485.
-
(2004)
IEEE ISSCC Dig. Tech. Papers
, vol.1
, pp. 484-485
-
-
Wu, C.-H.1
Liu, C.-S.2
Liu, S.-L.3
-
17
-
-
0034463672
-
A 70-MHz 70-dB-gain VGA with automatic continuous-time offset cancellation
-
C. B. Guo and H. C Luong, "A 70-MHz 70-dB-gain VGA with automatic continuous-time offset cancellation," in Proc. IEEE Midwest Symp. Circuits and Systems, 2000, pp. 306-309.
-
(2000)
Proc. IEEE Midwest Symp. Circuits and Systems
, pp. 306-309
-
-
Guo, C.B.1
Luong, H.C.2
-
18
-
-
0034297703
-
A 2-V 10.7 MHz CMOS limiting amplifier/RSSI
-
Oct
-
P.-C. Huang, Y.-H. Chen, and C-K. Wang, "A 2-V 10.7 MHz CMOS limiting amplifier/RSSI," IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 1474-1480, Oct. 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, Issue.10
, pp. 1474-1480
-
-
Huang, P.-C.1
Chen, Y.-H.2
Wang, C.-K.3
-
19
-
-
34548248796
-
A 1-V 100 MS/s 8-bit CMOS switched-opamp pipelined ADC using loading-free architecture
-
P. Wu, V. Cheung, and H. C Luong, "A 1-V 100 MS/s 8-bit CMOS switched-opamp pipelined ADC using loading-free architecture," in Symp. VLSI Circuits Dig. Tech. Papers, 2006, pp. 136-137.
-
(2006)
Symp. VLSI Circuits Dig. Tech. Papers
, pp. 136-137
-
-
Wu, P.1
Cheung, V.2
Luong, H.C.3
-
20
-
-
0032316466
-
A 12-bit intrinsic accuracy high-speed CMOS DAC
-
Dec
-
J. Bastos, A. M. Marques, M. S. J. Steyaert, and W. Sansen, "A 12-bit intrinsic accuracy high-speed CMOS DAC," IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1959-1969, Dec. 1998.
-
(1998)
IEEE J. Solid-State Circuits
, vol.33
, Issue.12
, pp. 1959-1969
-
-
Bastos, J.1
Marques, A.M.2
Steyaert, M.S.J.3
Sansen, W.4
-
22
-
-
0347498144
-
Impact of front-end non-idealities on bit error rate performance of WLAN-OFDM transceivers
-
Sep
-
Come et al, "Impact of front-end non-idealities on bit error rate performance of WLAN-OFDM transceivers," in Proc. RAWCON 2000, Sep. 2000, pp. 91-94.
-
(2000)
Proc. RAWCON 2000
, pp. 91-94
-
-
Come1
-
23
-
-
2942724554
-
Design and development of a 5.25 GHz software defined wireless OFDM communication platform
-
Jun
-
Lang et al, "Design and development of a 5.25 GHz software defined wireless OFDM communication platform," IEEE Commun. Mag., vol. 42, no. 6, pp. S6-12, Jun. 2004.
-
(2004)
IEEE Commun. Mag
, vol.42
, Issue.6
-
-
Lang1
|