A 5.5-GHz 16-mW fast-locking frequency synthesizer in 0.18-μm CMOS

2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Volumn , Issue , 2007, Pages 456-459

  Chiu, Wei Hao ^a   Chan, Tai Shun ^a   Lin, Tsung Hsien ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL FREQUENCY DIVIDERS; LOOP FILTERING; PHASE ERROR; SOLID-STATE CIRCUITS CONFERENCE;

CMOS INTEGRATED CIRCUITS; DIGITAL ARITHMETIC; DIGITAL SIGNAL PROCESSING; ELECTRIC CHARGE; FREQUENCY DIVIDING CIRCUITS; FREQUENCY SYNTHESIZERS; SIGNAL GENERATORS; VOLTAGE DIVIDERS;

PHASE LOCKED LOOPS;

EID: 51349136638     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2007.4425729     Document Type: Conference Paper

References (6)

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3. L. C. Liu and B. H. Li, "Fast locking scheme for PLL frequency synthesizer," Electronics Letters, Vol. 40, pp. 918-920, July. 2004.
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5. S. Pellerano, S. Levantino, and A. L. Lacaita, "A 13.5-mW 5-GHz Frequency Synthesizer with dynamic-logic frequency divider," IEEE JSSC, Vol. 39, No. 2, pp. 1445-1452, Feb. 2004.
6. T.-H. Lin and Y.-J. Lai, ""An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS PLL," IEEE J. Solid-State Circuits, vol. 42, pp. 340-349, Feb. 2007.