-
2
-
-
0029354845
-
Reduced pull-in time of phase-locked loops using a simple nonlinear phase detector
-
Aug.
-
P. Larsson, "Reduced pull-in time of phase-locked loops using a simple nonlinear phase detector," IEE Proc. Commun., vol. 142, no. 4, pp. 221-226, Aug. 1995.
-
(1995)
IEE Proc. Commun.
, vol.142
, Issue.4
, pp. 221-226
-
-
Larsson, P.1
-
4
-
-
0019079092
-
Charge-pump phase-locked loops
-
Nov.
-
F. M. Gardner, "Charge-pump phase-locked loops," IEEE Trans. Commun., vol. COM-28, pp. 1849-1858, Nov. 1980.
-
(1980)
IEEE Trans. Commun.
, vol.COM-28
, pp. 1849-1858
-
-
Gardner, F.M.1
-
6
-
-
0028465365
-
Analysis of a charge-pump PLL: A new model
-
July
-
M. V. Paemel, "Analysis of a charge-pump PLL: A new model," IEEE Trans. Commun., vol. 42, pp. 2490-2498, July 1994.
-
(1994)
IEEE Trans. Commun.
, vol.42
, pp. 2490-2498
-
-
Paemel, M.V.1
-
7
-
-
0343682744
-
Effectively reduced pull-in time of PLL with nonlinear phase comparator
-
Taiwan, R.O.C., Aug.
-
C. Y. Yang, W. C. Chung, and S. I. Liu, "Effectively reduced pull-in time of PLL with nonlinear phase comparator," in 8th VLSI/CAD Symp., Taiwan, R.O.C., Aug. 1997, pp. 205-208.
-
(1997)
8th VLSI/CAD Symp.
, pp. 205-208
-
-
Yang, C.Y.1
Chung, W.C.2
Liu, S.I.3
-
8
-
-
0343682745
-
-
National Semiconductor, Santa Clara, CA, Application Note, July
-
D. Byrd, C. Davis, and W. O. Keese, "A fast locking scheme for PLL frequency synthesizer," National Semiconductor, Santa Clara, CA, Application Note, July 1995.
-
(1995)
A Fast Locking Scheme for PLL Frequency Synthesizer
-
-
Byrd, D.1
Davis, C.2
Keese, W.O.3
-
9
-
-
0027615335
-
Fast CMOS nonbinary divider and counter
-
June
-
J. Yuan and C. Svensson, "Fast CMOS nonbinary divider and counter," Electron. Lett., vol. 29, pp. 1222-1223, June 1993.
-
(1993)
Electron. Lett.
, vol.29
, pp. 1222-1223
-
-
Yuan, J.1
Svensson, C.2
-
10
-
-
0031143856
-
A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL
-
May
-
S. Kim, K. Lee, Y. Moon, D. K. Jeong, Y. Choi, and H. K. Kim, "A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL," IEEE J. Solid-State Circuits, vol. 32, pp. 691-700, May 1997.
-
(1997)
IEEE J. Solid-state Circuits
, vol.32
, pp. 691-700
-
-
Kim, S.1
Lee, K.2
Moon, Y.3
Jeong, D.K.4
Choi, Y.5
Kim, H.K.6
-
11
-
-
0026954972
-
A PLL clock generator with 5- to 110-MHz of lock range for microprocessors
-
Nov.
-
I. A. Young, J. K. Greason, and K. L. Wong, "A PLL clock generator with 5- to 110-MHz of lock range for microprocessors," IEEE J. Solid-State Circuits, vol. 27, pp. 1599-1607, Nov. 1992.
-
(1992)
IEEE J. Solid-state Circuits
, vol.27
, pp. 1599-1607
-
-
Young, I.A.1
Greason, J.K.2
Wong, K.L.3
-
12
-
-
0030107330
-
Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks
-
Mar.
-
Q. Huang and R. Rogenmoser, "Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks," IEEE J. Solid-State Circuits, vol. 31, pp. 456-465, Mar. 1996.
-
(1996)
IEEE J. Solid-state Circuits
, vol.31
, pp. 456-465
-
-
Huang, Q.1
Rogenmoser, R.2
-
13
-
-
0030143673
-
A 1.2- GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flop
-
May
-
B. Chang, J. Park, and W. Kim, "A 1.2- GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flop," IEEE J. Solid-State Circuits, vol. 31, pp. 749-752, May 1996.
-
(1996)
IEEE J. Solid-state Circuits
, vol.31
, pp. 749-752
-
-
Chang, B.1
Park, J.2
Kim, W.3
-
14
-
-
0030145220
-
High-speed architecture for a programmable frequency divider and a dual-modulus prescaler
-
May
-
P. Larsson, "High-speed architecture for a programmable frequency divider and a dual-modulus prescaler," IEEE J. Solid-State Circuits, vol. 31, pp. 744-748, May 1996.
-
(1996)
IEEE J. Solid-state Circuits
, vol.31
, pp. 744-748
-
-
Larsson, P.1
-
15
-
-
0032186543
-
New dynamic flip-flops for high-speed dual-modulus prescaler
-
Oct.
-
C. Y. Yang, G. K. Dehng, J. M. Hsu, and S. I. Liu, "New dynamic flip-flops for high-speed dual-modulus prescaler," IEEE J. Solid-State Circuits, vol. 33, pp. 1568-1571, Oct. 1998.
-
(1998)
IEEE J. Solid-state Circuits
, vol.33
, pp. 1568-1571
-
-
Yang, C.Y.1
Dehng, G.K.2
Hsu, J.M.3
Liu, S.I.4
-
16
-
-
0031074269
-
A low-power CMOS dual-modulus prescaler for frequency synthesizer
-
Feb.
-
F. Piazza and Q. Huang, "A low-power CMOS dual-modulus prescaler for frequency synthesizer," IEICE Trans. Electron., vol. E80-C, pp. 314-319, Feb. 1997.
-
(1997)
IEICE Trans. Electron.
, vol.E80-C
, pp. 314-319
-
-
Piazza, F.1
Huang, Q.2
-
17
-
-
0031145163
-
A fully integrated low-noise 1-GHz frequency synthesizer design for mobile communication application
-
May
-
S. J. Lee, B. Kim, and K. Lee, "A fully integrated low-noise 1-GHz frequency synthesizer design for mobile communication application," IEEE J. Solid-State Circuits, vol. 32, pp. 760-765, May 1997.
-
(1997)
IEEE J. Solid-state Circuits
, vol.32
, pp. 760-765
-
-
Lee, S.J.1
Kim, B.2
Lee, K.3
-
18
-
-
0031170695
-
High-speed differential-voltage clamped current-mode ring oscillator
-
June
-
D. Y. Jeong, S. H. Chae, W. C. Song, and G. H. Cho, "High-speed differential-voltage clamped current-mode ring oscillator," Electron. Lett., vol. 33, pp. 1102-1103, June 1997.
-
(1997)
Electron. Lett.
, vol.33
, pp. 1102-1103
-
-
Jeong, D.Y.1
Chae, S.H.2
Song, W.C.3
Cho, G.H.4
|