A 5GHz phase-locked loop using dynamic phase-error compensation technique for fast settling in 0.18-μm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2009, Pages 128-129

  Chiu, Wei Hao ^a   Huang, Yu Hsiang ^a   Lin, Tsung Hsien ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Loop bandwidth; PLL; Settling time

Indexed keywords

CMOS PROCESSS; DYNAMIC PHASE; FREQUENCY DIVIDERS; FREQUENCY LOCKING; LOOP BANDWIDTH; PHASE ERROR; PLL; SETTLING TIME;

BANDWIDTH; ERROR COMPENSATION; SPURIOUS SIGNAL NOISE; VLSI CIRCUITS;

PHASE LOCKED LOOPS;

EID: 70449372022     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. X. F. Kuang and N. J. Wu, "A fast-settling PLL frequency synthesizer with direct frequency presetting," ISSCC Dig. Tech. Papers, pp. 741-750, Feb. 2006.
2. S. Shin et al., "4.2mW CMOS frequency synthesizer for 2.4GHz ZigBee application with fast settling time Performance," Microwave Symposium Digest, pp. 411-414, June. 2006.
3. C.-Y. Yang and S.-I. Liu, "Fast-switching frequency synthesizer with a discriminator-aided phase detector," IEEE J. Solid-State Circuits, vol. 35, pp. 1445-1452, Oct. 2000.
4. W.-H. Chiu et al., "A 5.5-GHz 16-mW fast-locking frequency synthesizer in 0.18-m CMOS," IEEE A-SSCC, pp. 456-459, Nov. 2007.