A 10μs fast switching PLL synthesizer for a GSM/EDGE base-station

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Keaveney, Mike ^a   Walsh, Patrick ^a   Tuthill, Mike ^a   Lyden, Colin ^a   Hunt, Bill ^a  

^a ANALOG DEVICES   (Ireland)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE PUMP CELLS; EDGE BASE-STATION; LOOP FILTERS; PHASE NOISE;

ACOUSTIC IMPEDANCE; AMPLIFIERS (ELECTRONIC); CASCADE CONNECTIONS; CHOPPERS (CIRCUITS); COMPUTER SIMULATION; ELECTRIC POTENTIAL; FREQUENCY HOPPING; GLOBAL SYSTEM FOR MOBILE COMMUNICATIONS; PHASE LOCKED LOOPS; RESISTORS; SIGNAL PROCESSING; SPACE DIVISION MULTIPLE ACCESS; VARIABLE FREQUENCY OSCILLATORS;

SWITCHING CIRCUITS;

EID: 2442666399     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Crowley, "Phase Locked Loop with Variable Gain and Bandwidth," US Patent 4, 156, 855.
2. Rhee, "Design of High Performance CMOS Charge Pumps in Phase-Locked Loops," IEEE International Symposium on Circuits and Systems, 1999.
3. Y. M. Greshishchev and P. Schvan, "SiCe Clock and Data Recovery IC with Linear-Type PLL for 10-Gb/s SONET Application," IEEE J. Solid-State Circuits, vol. 35, no. 9, pp. 1353-1359, Sept. 2000.
4. J. Bastos et al., "A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC," IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1959-1969, Dec. 1998.