Modeling of barrier-engineered charge-trapping NAND flash devices

IEEE Transactions on Device and Materials Reliability

Volumn 10, Issue 2, 2010, Pages 222-232

  Lue, Hang Ting ^a   Lai, Sheng Chih ^a   Hsu, Tzu Hsuan ^a   Du, Pei Ying ^a   Wang, Szu Yu ^a   Hsieh, Kuang Yeu ^a   Liu, Rich ^a   Lu, Chih Yuan ^a  

^a MACRONIX INTERNATIONAL CO LTD   (Taiwan)

Author keywords

Barrier engineering (BE); Barrier engineered silicon oxide nitride oxide silicon (BE SONOS); Charge trapping device; Incremental step pulse programming (ISPP); Modeling; NAND Flash; Tunneling

Indexed keywords

BAND GAPS; BARRIER COMPOSITIONS; BARRIER ENGINEERING; CAPPING LAYER; EXPERIMENTAL VALIDATIONS; HIGH-KAPPA; MULTILAYER BARRIERS; NAND FLASH; SILICON OXIDE NITRIDE OXIDE SILICONS; STEP PULSE; THEORETICAL MODELING; TIME EVOLUTIONS; TUNNELING CURRENT;

MULTILAYERS; NITRIDES; SILICON OXIDES;

TUNNELING (EXCAVATION);

EID: 77953263460     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2010.2041665     Document Type: Article

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