Reducing area overhead for error-protecting large L2/L3 caches

IEEE Transactions on Computers

Volumn 58, Issue 3, 2009, Pages 300-310

  Kim, Soontae ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

Cache memories; Error checking; SRAM

Indexed keywords

AREA EFFICIENT; AREA OVERHEAD; AVERAGE NUMBERS; CURRENT PROCESSORS; ERROR CORRECTING CODE; ERROR PROTECTION; ERROR-CHECKING; HIGH PERFORMANCE PROCESSORS; L2 CACHE; MAIN MEMORY; OFF-CHIP; ON CHIPS; ON-CHIP TRANSISTORS; PARITY CHECK CODES; PERFORMANCE DEGRADATION; SOFT ERROR; SUPERSCALAR PROCESSOR; TAG ARRAYS;

COMPUTER ARCHITECTURE; ERRORS; INFORMATION THEORY; MICROPROCESSOR CHIPS; STATIC RANDOM ACCESS STORAGE; TRANSISTORS;

CACHE MEMORY;

EID: 77953108559     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2008.174     Document Type: Article

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