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Volumn , Issue , 2010, Pages 628-635

A probabilistic boolean logic for energy efficient circuit and system design

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN LOGIC; CMOS DEVICES; DESIGN CIRCUITS; DESIGN PRINCIPLES; ENERGY EFFICIENT; INTERNATIONAL TECHNOLOGY; LOW ENERGIES; PROBABILISTIC BEHAVIOR; PROBABILISTIC DESIGN; SEMI CONDUCTOR; SYSTEM DESIGN; TECHNOLOGY SCALING; THEORETICAL BASIS;

EID: 77951217013     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2010.5419810     Document Type: Conference Paper
Times cited : (9)

References (31)
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    • (2006) Japanese Journal of Applied Physics , vol.45 , Issue.4 B , pp. 3307-3316
    • Korkmaz, P.1    Akgul, B.E.S.2    Chakrapani, L.N.3    Palem, K.V.4
  • 20
    • 38149086799 scopus 로고    scopus 로고
    • An analysis of internal parameter variations effects on nanoscaled gates
    • Jan.
    • F. Martorell, S. Cotofana, and A. Rubio. An analysis of internal parameter variations effects on nanoscaled gates. IEEE Transactions on Nanotechnology, 7(1):24-33, Jan. 2008.
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    • Martorell, F.1    Cotofana, S.2    Rubio, A.3
  • 22
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    • Moore, G.E.1
  • 23
    • 0042123349 scopus 로고    scopus 로고
    • Scaling limit of digital circuits due to thermal noise
    • K. Natori and N. Sano. Scaling limit of digital circuits due to thermal noise. Journal of Applied Physics, 83:5019-5024, 1998.
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    • Natori, K.1    Sano, N.2
  • 27
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.