Designing logic circuits for probabilistic computation in the presence of noise

Proceedings - Design Automation Conference

Volumn , Issue , 2005, Pages 485-490

  Nepal, K ^a   Bahar, R I ^a   Mundy, J ^a   Patterson, W R ^a   Zaslavsky, A ^a  

^a BROWN UNIVERSITY   (United States)

Author keywords

Markov random fields; Nanodevices; Noise immunity; Probabilistic computing; Reliability; Subthreshold operation

Indexed keywords

BENCHMARKING; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL METHODS; COMPUTER ARCHITECTURE; INTERCONNECTION NETWORKS; MARKOV PROCESSES; PROBABILITY DISTRIBUTIONS; PRODUCT DESIGN; SILICON; SPURIOUS SIGNAL NOISE;

MARKOV RANDOM FIELDS; NANODEVICES; NOISE IMMUNITY; PROBABILISTIC COMPUTING; SUBTHRESHOLD OPERATION;

LOGIC CIRCUITS;

EID: 27944449254     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dac.2005.193858     Document Type: Conference Paper

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