Variable partitioning and scheduling for MPSoC with virtually shared scratch pad memory

Journal of Signal Processing Systems

Volumn 58, Issue 2, 2010, Pages 247-265

  Zhang, Lei ^a   Qiu, Meikang ^b   Tseng, Wei Che ^c   Sha, Edwin H M ^c  

^a UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA   (China)

^b UNO College of Engineering   (United States)

^c The University of Texas at Dallas   (United States)

Author keywords

MPSoC; Scheduling; Scratch pad memory; Variable partitioning

Indexed keywords

ACCESS FREQUENCY; CHIP AREAS; CRITICAL COMPONENT; FOUR-CORE; GLOBAL VIEW; IN-PHASE; INITIAL SCHEDULE; INTEGRATED DATA; LIST-SCHEDULING; ON CHIP MEMORY; OPTIMAL VARIABLES; PERFORMANCE IMPROVEMENTS; POWER CONSUMPTION; ROTATION SCHEDULING; SCHEDULE LENGTH; SCRATCH PAD MEMORY; TASK-SCHEDULING;

MULTIPROCESSING SYSTEMS;

SCHEDULING ALGORITHMS;

EID: 77951208075     PISSN: 19398018     EISSN: 19398115     Source Type: Journal    
DOI: 10.1007/s11265-009-0362-3     Document Type: Article

References (24)

1. Banakar, R., Steinke, S., Lee, B.-S., Balakrishnan, M., & Marwedel, P. (2002). Scratchpad memory: A design alternative for cache on-chip memory in embedded systems. CODES '02: Proceedings of the tenth international symposium on Hardware/software codesign (pp. 73-78).
2. Motorola Corporation (1998). Mmc2001 reference manual. http://www.motorola.com/SPS/MCORE/info-documentation.htm.
3. Texas Instruments (1997). Tms370cx7x 8-bit microcontroller. http://www-s.ti.com/sc/psheets/spns034c/spns034c.pdf.
4. Motorola Corporation (2000). Cpu12 reference manual. http://e-www. motorola.com/brdata/PDFDB/MICROCONTROLLERS/16BIT/68HC12FAMILY/REFMAT/CPU12RM. pdf.
5. Kandemir, M., Ramanujam, J., Irwin, J., Vijaykrishnan, N., Kadayif, I., & Parikh, A. (2001). Dynamic management of scratch-pad memory space. In DAC '01: Proceedings of the 38th conference on Design automation (pp. 690-695).
6. Xue, C., Shao, Z., Liu, M., Qiu, M., & Sha E. H. M. (2006). Loop scheduling with complete memory latency hiding on multi-core architecture. In ICPADS '06: Proceedings of the 12th international conference on parallel and distributed systems (pp. 375-382).
7. Chen, T.-F., & Baer, J.-L. (1998). A performance study of software and hardware data prefetching schemes. International Symposium on Computer Architecture, 223-232.
8. F Chen TW ONeil EH-M Sha 2000 Optimizing overall loop schedules using prefetching and partitioning IEEE Transactions on Parallel and Distributed Systems 11 6 604 614 10.1109/71.862210
9. Z Wang EH-M Sha Y Wang 2002 Partitioning and scheduling dsp applications with maximal memory access hiding EURASIP Journal on Applied Signal Processing 9 926 935
10. Kandemir, M., Ramanujam, J., & Choudhury, A. (2002). Exploring shared scratch pad memory space in embedded multiprocessor system. In DAC '02: Proceedings of the 39th conference on design automation (pp. 219-224).
11. Terechko, A., Le Thénaff, E., & Corporaal, H. (2003). Cluster assignment of global values for clustered vliw processors. In CASES '03: Proceedings of the 2003 international conference on compilers, architecture and synthesis for embedded systems (pp. 32-40).
12. Suhendra, V., Raghavan, C., & Mitra, T. (2006). Integrated scratchpad memory optimization and task scheduling for mpsoc architectures. In CASES '06: Proceedings of the 2006 international conference on compilers, architecture and synthesis for embedded systems (pp. 401-410).
13. Ozturk, O., Chen, G., Kandemir, M., & Karakoy, M. (2006). An integer linear programming based approach to simultaneous memory space partitioning and data allocation for chip multiprocessors. In ISVLSI '06: Proceedings of the IEEE computer society annual symposium on emerging VLSI technologies and architectures (p. 50).
14. Vallerio, K. S., & Jha, N. K. (2003). Task graph extraction for embedded system synthesis. In VLSID '03: Proceedings of the 16th international conference on VLSI design (p. 480).
15. L-F Chao AS LaPaugh EH-M Sha 1997 Rotation scheduling: A loop pipelining algorithm IEEE Transactins on Computer-Aided Design 16 3 229 239 10.1109/43.594829
16. Aiken, A., & Nicolau, A. (1988). Optimal loop parallelization. SIGPLAN Notices, 23(7).
17. L-F Chao EH-M Sha 1997 Scheduling data-flow graphs via retiming and unfolding IEEE Transactions on Parallel and Distributed Systems 8 12 1259 1267 10.1109/71.640018
18. Ozturk, O., Kandemir, M., Chen, G., Irwin, M. J., & Karakoy, M. (2005). Customized on-chip memories for embedded chip multiprocessors. In ASP-DAC '05: Proceedings of the 2005 conference on Asia South Pacific design automation (pp. 743-748).
19. Meftali, S., Gharsalli, F., Rousseau, F., & Jerraya, A. A. (2001). An optimal memory allocation for application-specific multiprocessor system-on-chip. In ISSS '01: Proceedings of the 14th international symposium on systems synthesis (pp. 19-24).
20. PR Panda ND Dutt A Nicolau 2000 On-chip vs. off-chip memory: The data partitioning problem in embedded processor-based systems ACM Transactions on Design Automation of Electronic Systems 5 3 682 704 10.1145/348019.348570
21. JA Kahle MN Day HP Hofstee CR Johns TR Maeurer D Shippy 2005 Introduction to the cell multiprocessor IBM Journal of Research and Development 49 4/5 589 604
22. Guthaus, M. R., Ringenberg, J. S., Ernst, D., Austin, T. M., Mudge, T., & Brown R. B. (2001). Mibench: A free, commercially representative embedded benchmark suite. In WWC '01: Proceedings of the workload characterization, 2001. WWC-4. 2001 IEEE international workshop (pp. 3-14).
23. Valgrind (2009). Valgrind homepage. http://www.valgrind.org.
24. Chen G., Ozturk, O., Kandemir, M., & Irwin, M. J. (2006). Multi-level on-chip memory hierachy design for embedded chip multiprocessor. In ICPADS '06: Proceedings of the 12th international conference on parallel and distributed system (pp. 383-390).