Optimizing overall loop schedules using prefetching and partitioning

IEEE Transactions on Parallel and Distributed Systems

Volumn 11, Issue 6, 2000, Pages 604-614

  Chen, Fei ^a   O'Neil, Timothy W ^a,b   Sha, Edwin H M ^a,b  

^a University of Notre Dame   (United States)

^b IEEE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARITHMETIC LOGIC UNIT; DATA PREFETCHING; LOOP PIPELINING TECHNIQUE; PARTITION SCHEDULING WITH PREFETCHING;

DATA STORAGE EQUIPMENT; DATA TRANSFER; DIGITAL SIGNAL PROCESSING; OPTIMIZATION; PIPELINE PROCESSING SYSTEMS; SCHEDULING;

PARALLEL ALGORITHMS;

EID: 0034206930     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/71.862210     Document Type: Article

References (18)

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