Partitioning and scheduling DSP applications with maximal memory access hiding

Eurasip Journal on Applied Signal Processing

Volumn 2002, Issue 9, 2002, Pages 926-935

  Wang, Zhong ^a   Sha, Edwin Hsing Mean ^b   Wang, Yuke ^b  

^a University of Notre Dame   (United States)

^b The University of Texas at Dallas   (United States)

Author keywords

Balanced partition scheduling; Initial data; Loop pipelining; Maximal overlap

Indexed keywords

ALGORITHMS; COMPUTER OPERATING SYSTEMS; DATA STORAGE EQUIPMENT; EMBEDDED SYSTEMS; ITERATIVE METHODS; SCHEDULING;

MEMORY LATENCY; MEMORY TRAFFIC;

DIGITAL SIGNAL PROCESSING;

EID: 0037803454     PISSN: 11108657     EISSN: None     Source Type: Journal    
DOI: 10.1155/S1110865702205041     Document Type: Article

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