Multi-level on-chip memory hierarchy design for embedded chip multiprocessors

Proceedings of the International Conference on Parallel and Distributed Systems - ICPADS

Volumn 1, Issue , 2006, Pages 8-15

  Ozturk, Ozcan ^a   Kandemir, Mahmut ^a   Irwin, Mary Jane ^a   Tosun, Suleyman ^b  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

^b SELCUK UNIVERSITY   (Turkey)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; DATA ACQUISITION; EMBEDDED SYSTEMS; INTEGER PROGRAMMING; LINEAR PROGRAMMING; MICROPROCESSOR CHIPS;

DATA ALLOCATIONS; INTEGER LINEAR PROGRAMMING (ILP) SOLUTION; ON CHIP MEMORY PARTITIONING;

PARALLEL PROCESSING SYSTEMS;

EID: 34047243226     PISSN: 15219097     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPADS.2006.66     Document Type: Conference Paper

References (18)

1. F. Angiolini, L. Benini, and A. Caprara. Polynomial-Time Algorithm for On-Chip Scratch-Pad Memory Partitioning. In Proceedings of CASES, San Jose, CA, 2003.
2. L. Benini, A. Macii, E. Macii, and M. Poncino. Increasing energy efficiency of embedded systems by application-specific memory hierarchy generation. IEEE Design & Test of Computers, pages 74-85, April-June, 2000.
3. Y. Cao, H. Tomiyama, T. Okuma, and H. Yasuura. Data Memory Design Considering Effective Bit-width for Low-Energy Embedded Systems. In Proceedings of ISSS, Kyoto, Japan, October 2002.
4. F. Catthoor, S. Wuytack, E. D. Greef, F. Balasa, L. Nachtergaele, and A. Vandecappelle. Custom Memory Management Methodology - Exploration of Memory Organization for Embedded Multimedia System Design, Kluwer Academic Publishers, 1998.
5. F. Gharsalli, S. Meftali, F. Rousseau, and A. A. Jerraya. Automatic Generation of Embedded Memory Wrapper for Multiprocessor SoC. In Proceedings of DAC, New Orleans, Louisiana, 1999.
6. M. Kandemir, J. Ramanujam, M. Irwin, N. Vijaykrishnan, I. Kadayif, and A. Parikh. Dynamic Management of Scratch-Pad Memoiy Space. In Proceedings of DAC, Las Vegas, NV, June 2001.
7. M. Kandemir, O. Ozturk, and M. Karakoy. Dynamic On-Chip Memory Management for Chip Multiprocessors. In Proceedings of CASES, Washington D.C., September 2004.
8. S. Meftali, F. Gharsalli, F. Rousseau, and A. A. Jerraya. An Optimal Memory Allocation for Application-Specific Multiprocessor System-on-Chip. In Proceedings of the International Symposium on Systems Synthesis, Montreal, Canada, 2001.
9. G. Nemhauser, L. Wolsey. Integer and Combinatorial Optimization, Wiley-lnterscience Publications, 1988.
10. P. R. Panda and L. Chitturi. An Energy-Conscious Algorithm for Memory Port Allocation. In Proceedings of ICCAD, San Jose, California, November 2002.
11. P. R. Panda, N. D. Dutt, and A. Nicolau. Architectural Exploration and Optimization of Local Memory in Embedded Systems. In Proceedings of ISSS, Antwerp, Belgium, September 1997.
12. A. Ramachandran and M. F. Jacome. Xtream-Fit: An Energy-Delay Efficient Data Memory Subsystem for Embedded Media Processing. In Proceedings of DAC, Anaheim, CA, June 2003.
13. G. Reinman and N. P. Jouppi. CACTI 2.0: An Integrated Cache Timing and Power Model. Compaq, WRL, Research Report 2000/7, February 2000.
14. W.-T. Shiue and C. Chakrabarti. Memory Exploration for Low-Power Embedded Systems. In Proceedings of DAC, New Orleans, LA, 1999.
15. SIMICS Tool-set, http://www.virtutech.com/
16. G. E. Suh, L. Rudolph, and S. Devadas. Dynamic Partitioning of Shared Cache Memory, Journal of Supercomputing, 2002.
17. S. Udayakumaran and R. Barua. Compiler-Decided Dynamic Memory Allocation for Scratch-Pad Based Embedded Systems. In Proceedings of CASES, San Jose, CA, 2003.
18. Xpress-MP, http://www.dashoptimization.com/pdf/Mosell.pdf, May 2002.