Loop scheduling with complete memory latency hiding on multi-core architecture

Proceedings of the International Conference on Parallel and Distributed Systems - ICPADS

Volumn 1, Issue , 2006, Pages 375-382

  Xue, Chun ^a   Shao, Zili ^b   Liu, Meilin ^a   Qiu, Meikang ^a   Sha, Edwin H M ^a  

^a The University of Texas at Dallas   (United States)

^b HONG KONG POLYTECHNIC UNIVERSITY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; ITERATIVE METHODS; PROGRAM PROCESSORS; SCHEDULING; STORAGE ALLOCATION (COMPUTER);

COMPLETE MEMORY LATENCY; ITERATIONAL RETIMING; LOOP SCHEDULING; MEMORY LATENCIES;

COMPUTER ARCHITECTURE;

EID: 34047199043     PISSN: 15219097     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPADS.2006.58     Document Type: Conference Paper

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