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Volumn , Issue , 2009, Pages 301-306

New class of tests for open faults with considering adjacent lines

Author keywords

Adjacent lines; Open fault; Ordered pair of tests(OPT); Test pattern generation

Indexed keywords

CIRCUIT PARAMETER; DEEP SUB-MICRON; EXCITATION FUNCTION; FAULT COVERAGES; LAYOUT INFORMATION; OPEN FAULTS; STUCK-AT FAULTS; TEST PATTERN GENERATIONS; THRESHOLD FUNCTIONS;

EID: 77951150874     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2009.39     Document Type: Conference Paper
Times cited : (3)

References (15)
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    • Chen, W.1    Gupta, S.K.2    Breuer, M.A.3
  • 9
    • 33947617816 scopus 로고    scopus 로고
    • Interconnect open defect diagnosis with physical information
    • Z.Zou, W.-T.Cheng, and S.M.Reddy," Interconnect open defect diagnosis with physical information", Proc. Asian Test Symp., pp.203-208, 2006
    • (2006) Proc. Asian Test Symp. , pp. 203-208
    • Zou, Z.1    Cheng, W.-T.2    Reddy, S.M.3
  • 12
    • 67249100226 scopus 로고    scopus 로고
    • Test generation for interconnect opens
    • paper 33.1
    • X.Lin and J.Rajski, "Test generation for interconnect opens", Proc. Int. Test Conf., Paper 33.1, 2008
    • (2008) Proc. Int. Test Conf.
    • Lin, X.1    Rajski, J.2
  • 13
    • 67249161649 scopus 로고    scopus 로고
    • Extraction, simulation and test generation for interconnect open defects based on enhanced aggressor-victim model
    • 33.3
    • S. Hillebrecht, I. Polian, P. Engelke, B. Becker, M. Keim, W-T. Cheng, "Extraction, simulation and test generation for interconnect open defects based on enhanced aggressor-victim model", Proc. Int. Test Conf., Paper 33.3, 2008
    • (2008) Proc. Int. Test Conf.
    • Hillebrecht, S.1    Polian, I.2    Engelke, P.3    Becker, B.4    Keim, M.5    Cheng, W.-T.6
  • 15
    • 0029536659 scopus 로고
    • Costeffective generation of minimal test sets for stuck-at faults in combinational logic circuits
    • S. Kajihara, I. Pomeranz, K. Kinoshita, S.M. Reddy, "Costeffective generation of minimal test sets for stuck-at faults in combinational logic circuits", IEEE Trans. on Computer-Aided Design, vol. 14(12), pp.1496-1504, 1995.
    • (1995) IEEE Trans. on Computer-aided Design , vol.14 , Issue.12 , pp. 1496-1504
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.