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Volumn , Issue , 2007, Pages 39-44

Clues for modeling and diagnosing open faults with considering adjacent lines

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATIONS; DSM CIRCUITS; LOGIC VALUES; MANUFACTURING TECHNOLOGIES; OPEN FAULTS; SIMULATION RESULTS;

EID: 48049105547     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2007.4387980     Document Type: Conference Paper
Times cited : (15)

References (9)
  • 1
    • 0036446204 scopus 로고    scopus 로고
    • On Testing Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout
    • S. M. Reddy, I. Pomeranz, H. Tang, S. Kajihara, and K. Kinoshita, "On Testing Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout," Proc. Int. Test Conf., pp.83-87, 2002.
    • (2002) Proc. Int. Test Conf , pp. 83-87
    • Reddy, S.M.1    Pomeranz, I.2    Tang, H.3    Kajihara, S.4    Kinoshita, K.5
  • 2
    • 0033743138 scopus 로고    scopus 로고
    • A Technique for Logic Fault Diagnosis of Interconnect Open Defects
    • S. Venkataraman and S. B. Drummonds, "A Technique for Logic Fault Diagnosis of Interconnect Open Defects," Proc. VLSI Test Symp., pp.313-318, 2000.
    • (2000) Proc. VLSI Test Symp , pp. 313-318
    • Venkataraman, S.1    Drummonds, S.B.2
  • 3
    • 0037379321 scopus 로고    scopus 로고
    • Symbolic Injec-and-Evaluation Paradigm for Byzantine Fault Diagnosis
    • S-Y. Huang, "Symbolic Injec-and-Evaluation Paradigm for Byzantine Fault Diagnosis," Journal of Electronic Testing Theory and Applications, vol. 19, pp.161-172, 2003.
    • (2003) Journal of Electronic Testing Theory and Applications , vol.19 , pp. 161-172
    • Huang, S.-Y.1
  • 5
    • 0033319644 scopus 로고    scopus 로고
    • Voltage- and Current-Based Fault Simulation for Interconnect Open Defects
    • H. Konuk, "Voltage- and Current-Based Fault Simulation for Interconnect Open Defects," IEEE Trans. on Computer-Aided Design, vol.18, no. 12, pp.1768-1779, 1999.
    • (1999) IEEE Trans. on Computer-Aided Design , vol.18 , Issue.12 , pp. 1768-1779
    • Konuk, H.1
  • 6
    • 0025480229 scopus 로고
    • Diagnosing CMOS Bridging Faults with Stuck-at Fault Dictionaries
    • S. D. Millman, E. J. McCluskey, and J. M. Acken, "Diagnosing CMOS Bridging Faults with Stuck-at Fault Dictionaries," Proc. Int. Test Conf., pp.860-870, 1990.
    • (1990) Proc. Int. Test Conf , pp. 860-870
    • Millman, S.D.1    McCluskey, E.J.2    Acken, J.M.3
  • 9
    • 0033336301 scopus 로고    scopus 로고
    • Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information
    • J. G-Dastidar, D. Das and N. A. Touba, "Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information," Proc. Int. Test Conf., pp.95-102, 1999.
    • (1999) Proc. Int. Test Conf , pp. 95-102
    • G-Dastidar, J.1    Das, D.2    Touba, N.A.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.