Fault effect of open faults considering adjacent signal lines in a 90 nm IC

Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems

Volumn , Issue , 2009, Pages 91-96

  Yotsuyanagi, Hiroyuki ^a   Hashizume, Masaki ^a   Tsutsumi, Toshiyuki ^b   Yamazaki, Koji ^b   Aikyo, Takashi ^c   Higami, Yoshinobu ^c   Takahashi, Hiroshi ^c   Takamatsu, Yuzo ^c  

^a UNIVERSITY OF TOKUSHIMA   (Japan)

^b MEIJI UNIVERSITY   (Japan)

^c EHIME UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK CIRCUITS; COUPLING CAPACITANCES; FAULT EFFECTS; OPEN FAULTS; SIGNAL LINES; THREE LAYERS; TRANSMISSION GATES; WEIGHTED SUMS;

INTEGRATED CIRCUITS;

EMBEDDED SYSTEMS;

EID: 62949146532     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSI.Design.2009.60     Document Type: Conference Paper

References (13)

1. D. Arumi, R. Rodriguez-Montanes, and J. Figueras. Experimental characterization of CMOS interconnect open defects. IEEE Trans. on Computer-Aided Design, 27(1):123-136, Jan 2008.
2. R. Gomez, A. Giron, and V. Champac. Test of interconnection opens considering coupling signals. Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pages 247-258, 2005.
3. M. Hashizume, M. Ichimiya, H. Yotsuyanagi, and T. Tamesada. CMOS open defect detection by supply current measurement under time-variable electric field supply. IEICE transactions on information and systems, E85-D(10):1542-1550, Oct. 2002.
4. M. Hashizume, Y. Yamada, H. Yotsuyanagi, T. Tsutsumi, K. Yamazaki, Y. Higami, H. Takahashi, and Y. Takamatsu. Fault analysis of interconnect opens in 90nm CMOS ICs with device simulator. Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pages 249-252, 2008.
5. J. C.-M. Li, C.-W. Tseng, and E. McCluskey. Testing for resistive opens and stuck opens. Proc. International Test Conference, pages 1049-1058, 2001.
6. E. J. McCluskey and C.-W. Tseng. Stuck-fault tests vs. actual defects. Proc. International Test Conference, pages 336-342, 2000.
7. S. M. Reddy, I. Pomeranz, H. Tang, S. Kajihara, and K. Kinoshita. On testing of interconnect open defects in combinational logic circuits with stems of large fanout. Proc. International Test Conference, page 83, 2002.
8. Y. Sato, I. Yamazaki, H. Yamanaka, T. Ikeda, and M. Takakura. A persistent diagnostic technique for unstable defects. Proc. International Test Conference, pages 242-249, 2002.
9. S. Spinner, I. Polian, P. Engelke, B. Becker, M. Keim, and W.-T. Cheng. Automatic test pattern generation for interconnect open defects. Proc. VLSI Test Symp., pages 181-186, 2008.
10. H. Takahashi, Y. Higami, S. Kadoyama, T. Aikyo, Y. Takamatsu, K. Yamazaki, T. Tsutsumi, H. Yotsuyanagi, and M. Hashizume. Clues for modeling and diagnosing open faults with considering adjacent lines. Proc. Asian Test Symp., pages 39-44, 2007.
11. H. Takahashi, Y. Higami, T. Kikkawa, T. Aikyo, Y. Takamatsu, K. Yamazaki, T. Tsutsumi, H. Yotsuyanagi, and M. Hashizume. Test generation and diagnostic test generation for open faults with considering adjacent lines. Proc. International Symposium on Defect and Fault-Tolerance in VLSI Systems, pages 243-251, Sept. 2007.
12. K. Yamazaki, T. Tsutsumi, H. Takahashi, Y. Higami, T. Aikyo, H. Yotsuyanagi, M. Hashizume, and Y. Takamatsu. A novel approach for improving the quality of open fault diagnosis. VLSI Design 2009, 2009. (to appear).
13. A. Zenteno, V. H. Champac, and J. Figueras. Detectability conditions of full opens in the interconnections. Journal of Electronic Testing: Theory and Applications, 17:85-95, 2001.