Test generation and diagnostic test generation for open faults with considering adjacent lines

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2007, Pages 243-251

  Takahashi, Hiroshi ^a   Higami, Yoshinobu ^a   Kikkawa, Toru ^a   Aikyo, Takashi ^a   Takamatsu, Yuzo ^a   Yamazaki, Koji ^b   Tsutsumi, Toshiyuki ^b   Yotsuyanagi, Hiroyuki ^c   Hashizume, Masaki ^c  

^a EHIME UNIVERSITY   (Japan)

^b MEIJI UNIVERSITY   (Japan)

^c UNIVERSITY OF TOKUSHIMA   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADJACENT LINES; BENCHMARK CIRCUIT; DIAGNOSTIC TEST GENERATION; DIAGNOSTIC TESTS; FAULT COVERAGES; OPEN DEFECTS; STUCK-AT FAULT TESTS; TEST GENERATIONS;

DEFECTS; DESIGN FOR TESTABILITY; INTEGRATED CIRCUIT TESTING;

FAULT TOLERANCE;

EID: 57249098479     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFT.2007.11     Document Type: Conference Paper

References (9)

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