On tests to detect via opens in digital CMOS circuits

Proceedings - Design Automation Conference

Volumn , Issue , 2008, Pages 840-845

  Reddy, Sudhakar M ^a   Pomeranz, Irith ^b   Liu, Chen ^a  

^a UNIVERSITY OF IOWA   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

Constrained stuck at tests; DFT; Open defects; Test generation

Indexed keywords

CIRCUIT PARAMETERS; CONSTRAINED STUCK-AT TESTS; DFT; OPEN DEFECTS; TEST GENERATION;

ARSENIC COMPOUNDS; COMPUTER AIDED DESIGN; DIGITAL ARITHMETIC; DIGITAL CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC NETWORK PARAMETERS; INDUSTRIAL ENGINEERING; TESTING; VLSI CIRCUITS;

LOGIC CIRCUITS;

EID: 51549118309     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555936     Document Type: Conference Paper

References (17)

1. W. Maly, P.K. Nag and P. Nigh, "Testing oriented analysis of CMOS ICs with opens", IEEE TCAD, Nov. 1988, pp. 344-347.
2. R. Rodriguez-Montanes and J. Figueras, "Electrical and Topological Characterization of Interconnect Open Defects", IEEE international Workshop on Current and Defective Based Testing, 2005.
3. H. Konuk, "Voltage and current based fault simulation for interconnect open defects", IEEE TCAD, Dec. 1999, pp. 1768-1779.
4. M. Renovell and G.M. Cambon, "Electrical Analysis of Floating-Gate Fault", IEEE TCAD Nov. 1992, pp. 1450-1458.
5. H. Konuk and F.J. Ferguson, "Oscillation and sequential behavior caused by opens in the routing in digital CMOS circuits", IEEE TCAD, Nov. 1998, pp. 1200-1210.
6. H. Konuk and F.J. Ferguson, "An Unexpected factor in Testing for CMOS Opens: The Die Surface", Proc. VTS 1996, pp. 422-429.
7. V.H. Champac and A. Zenteno, "Detectability Conditions for Interconnect Open Defects", Proc. VTS 2005, pp. 305-311.
8. D. Arumi, R. Rodriguez-Montanes and J. Figueras, "Defective Behaviours of Resistive Opens in Interconnect Lines", Proc. ETS 2005, pp. 28-33.
9. S. M. Reddy, I. Pomeranz, H. Tang, S. Kajihara and K. Kinoshita, "On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout", Proc. ITC 2002, pp. 83-89.
10. R.D. Blanton, K.N. Dwarakanath and A.B. Shah, "Analyzing the Effectiveness of Multiple-Detect Test Sets", Proc. ITC 2003, pp. 876-885.
11. R. Gomez, A. Giron and V. Champac, "Test of Interconnect Opens Considering Coupling Signals", Proc. DFTS 2005, pp. 247-255.
12. J.E. Nelson, J.G. Brown, R. Desineni and R.D. Blanton, "Multiple-Detect ATPG Based on Physical Neighborhoods", Proc. DAC 2006, pp. 1099-1102.
13. S. Rafiq, A. Ivanov, Y. Bertrand, F. Azias, and M. Renovell, "Testing for Floating Gates Defects in CMOS Circuits", Proc. ATS 1998, pp. 228-236.
14. R. Aitken, et al., "Defect-Oriented Test", Tutorial at ITC 2000, pp. 62-68.
15. W.A. Pleskacz, C.H. Quyang and W. Maly, "A DRC-based Algorithm for Extraction of Critical Areas for Opens in Large VLSI Circuits", IEEE TCAD, Feb. 1999, pp. 151-162.
16. http://ece.tamu.edu/̃xiang/iscas.html
17. J.M. Howard, S.M. Reddy and I. Pomeranz, "Circuit Parameter Independent Tests for Interconnect Opens", Technical Report, ECE Department, Univeristy of Iowa, Iowa City, IA.